Chisel

问题 Are there any fixed point libraries in Chisel HDL which could be used to perform basic arithmetic operations such as add, subtract, multiply and divide? 回答1: I believe a Fixed class is under active development. Take a look at Fixed.scala in the Chisel repo. 来源： https://stackoverflow.com/questions/35237958/fixed-point-arithmetic-in-chisel-hdl

问题 I'm a new user of chisel. I tried to install chisel on my machine. According to the git, first I cloned chisel and then I went to hello directory and enter make . But I got the below error: set -e -o pipefail; sbt -Dsbt.log.noformat=true -DchiselVersion="latest.release" "run Hello --genHarness --compile --test --backend c --vcd " | tee Hello.out /bin/sh: 1: set: Illegal option -o pipefail make: *** [Hello.out] Error 2 I'm using sbt-0.13.8 and scala 2.11.6 回答1: If you try without the command

问题 In chisel-tutorial ,after I ran sbt "run Hello --backend v --compile --test --genHarness --vcd" I got the Hello.v ,Hello-harness.v ,vpi_user.cc files How can I test the Hello.v file? What is the usage of vpi_user.cc? 回答1: To test your design in VCS you can use the two verilog files generated: Hello.v : Your Chisel design generated in Verilog Hello-harness.v : Your testbench code in Verilog (generated by --genHarness option). Of course you have to modify it to improve your test. 来源： https:/

问题 I would like to find out how it is possible to initialize a Module , depending on a value. So I have a config.extend value which will decide if the core will instantiate of the Core or ExtendedCore module. However I am getting the error "value := is not a member of Sodor.core". val extend = 1 val core = Module(new Core(data_address)) if(extend==1){ core := Module(new ExtendedCore(data_address)) } What is the proper way to intialize a Module depending on the statement, like in this case?

问题 I already asked a similar question for chisel2 in case of C++ backend. But now I'm using The template example with iotester (peek and poke) with chisel3. With the following code (can be found on my github project page): class TapTempoUnitTester(t: TapTempo) extends PeekPokeTester(t) { private val tptmp = t def pushbutton(button: Bool) { poke(button, 0) step(1) poke(button, 1) step(10) poke(button, 0) } val tclk = 10 val tus = 1000/tclk val tms = 1000*tus val ts = 1000*tms //0 pushbutton(tptmp

问题 This Chisel code works ok: chiselMainTest(Array[String]("--backend", "c", "--genHarness"), () => Module( new Cache(nways = 16, nsets = 32) )){c => new CacheTests(c)} However this one - a small variation - produces run-time error: val cache_inst = new Cache(nways = 16, nsets = 32) chiselMainTest(Array[String]("--backend", "c", "--genHarness"), () => Module(cache_inst)){c => new CacheTests(c)} [error] (run-main) java.util.NoSuchElementException: head of empty list java.util

问题 Chisel generate always blocks with only clock in sensivity list : always @posedge(clk) begin [...] end Is it possible to configure Module to use an asynchronous reset and generate an always block like this ? always @(posedge clk or posedge reset) begin [...] end 回答1: It looks like this question has been asked elsewhere on the interwebs... the answer is that Chisel does not natively have this functionality built into it. It looks like the way to do this in Chisel is to use synchronous resets:

问题 I was reading source code of rocket chip, in rocc.scala file in rocket/src/main/scala/ there is an example AccumulatorExample for using rocc . At first part of the code there is a function Queue() that I couldn't figure out what it's doing? val n = 4 val regfile = Mem(UInt(width = params(XprLen)), n) val busy = Vec.fill(n){Reg(init=Bool(false))} val cmd = Queue(io.cmd) val funct = cmd.bits.inst.funct val addr = cmd.bits.inst.rs2(log2Up(n)-1,0) val doWrite = funct === UInt(0) val doRead =

问题 I'm learning Chisel following the documentation on Github Thus far, everything worked flawlessly. But i'm stuck at chapter 13, "Functional Module Creation" I can't get the code to work . I created all my .scala classes in a copy of the chisel-template-project. Here is what i wrote / copied to create a Mux4 with variable bit width : /chisel-template/src/main/scala/ Mux4.scala import Chisel._ class Mux4(w: Int) extends Module { val io = IO(new Bundle { val sel = UInt(INPUT, 2) val in0 = UInt

问题 Is there some built in test or tools for formal verification of chisel or firrtl design vs generated verilog? On which concepts verilog backend is build? Is there any bugs in it? 回答1: There is no built-in formal verification support in Chisel and FIRRTL. There is no proof of work for the compiler or backend. As with any traditional compiler, there are certainly bugs although we do our best to catch and fix them. We are currently using Yosys to perform LEC on a few instances of FIRRTL circuits