Chisel

问题 I'm new to chisel. Currently I'm following chisel-tutorial wiki using chisel3. After cloning the chisel project template linked there, I tried to test and generate verilog output from GCD.scala source file. I got the following error. > run --v java.lang.RuntimeException: No main class detected. at scala.sys.package$.error(package.scala:27) [trace] Stack trace suppressed: run last compile:run for the full output. [error] (compile:run) No main class detected. [error] Total time: 0 s, completed

问题 I'm new to chisel. Currently I'm following chisel-tutorial wiki using chisel3. After cloning the chisel project template linked there, I tried to test and generate verilog output from GCD.scala source file. I got the following error. > run --v java.lang.RuntimeException: No main class detected. at scala.sys.package$.error(package.scala:27) [trace] Stack trace suppressed: run last compile:run for the full output. [error] (compile:run) No main class detected. [error] Total time: 0 s, completed

问题 As tile, how to cast UInt to SInt value in Chisel3 in right way? ig: val opC = RegInit(0.U(64.W)) val result = RegInit(0.U(64.W)) result := Mux(opC.toSInt > 0.S, opC, 0.U) 回答1: It depends on if you want to reinterpret as an SInt (same width), or actually cast (ie. casting an 8-bit UInt results in a 9-bit SInt). You should reinterpret a UInt to an SInt by calling .asSInt on the UInt. eg. opC.asSInt , the result will be the same width. You should cast a UInt to an SInt by calling .zext on the

问题 It is possible to make a partial assignment to a vector IO as follows: import chisel3._ class example_1 extends Module { val io = IO(new Bundle { val in1 = Input(Vec(4, Bool()) val out1 = Output(Vec(4, Bool()) }) for (I <- 0 to 3){ io.out1(I) := io.in1(I) } } Is it possible to make a partial assignment to a multi-bit slice of a vector. The following code doesn't work import chisel3._ class example_1 extends Module { val io = IO(new Bundle { val in1 = Input(Vec(4, Bool()) val out1 = Output(Vec

问题 I'm trying to use Chisel on a "real-world" project and I'm writing the testbench code part in C++. That work well, I can see all my dumped signals in the dump.vcd file with gtkwave. But I have a problem for timescale, by default, the function module->dump() record signal with timescale at 1ps: $timescale 1ps $end Do you know how to change it ? The only way I found to change it in the testbench C++ code is to re-open the vcd after closing it and modify the first line : #define CYCLE_PERIOD_NS

问题 There is a Queue in ChiselUtil class that is described in manual as : // Generic hardware queue. Required // parameter entries controls the // depth of the queues. The width of // the queue is determined from the // inputs. // Example usage: // val q = new Queue(UInt(), 16) // q.io.enq <> producer.io.out // consumer.io.in <> q.io.deq class Queue[T <: Data] (type: T, entries: Int, pipe: Boolean = false, flow: Boolean = false flushable: Boolean = false) extends Module But in the scala code,

问题 I have recently started work in scala, and am required to create an implementation of MD5. It is my understanding that MD5 requires unsigned types, which scala does not come with. As I will soon begin Chisel, which does have unsigned types, I decided to implement its library. Everything appears good so far, except when doing the below bitwise operations, my F value becomes -271733879, which causes an error "Caused by: java.lang.IllegalArgumentException: requirement failed: UInt literal

问题 I want to write a simple chisel3 blinking led design on my AC701 kit (artix7). But to do that I have to instantiate a clock input differential buffer. Xilinx give the following verilog template to do that : IBUFDS #( .DIFF_TERM("TRUE"), .IOSTANDARD("DEFAULT") ) IBUFDS1_inst ( .O(clock1), // Clock buffer .I(clock1_p), // Diff_p clock .IB(clock1_n) // Diff_n clock ); I read on chisel documentation that I have to use «blackbox» class to instantiate it. But I can't do it. I tried this : class

问题 I want to instantiate a one dimensional array of element, and element extends Module. How would I do this? If I say my best guess, which is: val elements = Vec( 64, new element ) I get the following error message: [error] /Users/mykland/work/chisel/array.scala:20: overloaded method value apply with alternatives: [error] [T <: Chisel.Data](n: Int, gen: => T)Chisel.Vec[T] <and> [error] [T <: Chisel.Data](elt0: T, elts: T*)Chisel.Vec[T] <and> [error] [T <: Chisel.Data](gen: => T, n: Int)Chisel

问题 Does Chisel support matrix operations such as addition, multiplication, transposition, etc.? If not, what is the best way to implement them? How about vectors? 回答1: Chisel does not support matrix operations. It is a DSL for writing hardware generators that implement of such operations. For examples of specialized math hardware generators see: Hwacha: A hardware vector unit and DspTools: a set of math tools 回答2: Yes, you can do matrix operations in Chisel with the help of vectors. The code I