How to change timescale of VCD file dumped?

问题

I'm trying to use Chisel on a "real-world" project and I'm writing the testbench code part in C++. That work well, I can see all my dumped signals in the dump.vcd file with gtkwave.

But I have a problem for timescale, by default, the function module->dump() record signal with timescale at 1ps:

$timescale 1ps $end

Do you know how to change it ?

The only way I found to change it in the testbench C++ code is to re-open the vcd after closing it and modify the first line :

#define CYCLE_PERIOD_NS   10
FILE *f = fopen("./dump.vcd", "w");
module->set_dumpfile(f);
[...]
/*several module->dump() call */
[...]
if (f) {
    fclose(f);

    std::string line;
    std::ifstream input("./dump.vcd");
    std::ofstream output("./tmp.vcd");
    std::getline(input, line);
    output << "$timescale " << CYCLE_PERIOD_NS << "ns $end" << endl;
    while(std::getline(input, line)) {
        output << line << endl;
    }
    rename("./tmp.vcd", "./dump.vcd");
}

回答1:

The method I given work only for C++ backend, the problem remain the same if we use chisel class Test. I modified Chisel code to add the period in implicitClock object. Then I modified the Vcd class to dump VCD with the correct period value. You can see the patch here.

Then to change timescale you just have to add the following line in your top Chisel module:

class myModule extends Module {
[...]
Driver.implicitClock.period = "10ns"
[...]
}

This patch has been commited for the version 2.2.28 of Chisel.

来源：https://stackoverflow.com/questions/30886309/how-to-change-timescale-of-vcd-file-dumped

标签

c++

fpga

Chisel