How to test the verilog module generated by Chisel in VCS ? How does vpi_uer.cc work in chisel?

问题

In chisel-tutorial ,after I ran

sbt "run Hello --backend v --compile --test --genHarness --vcd"

I got the Hello.v ,Hello-harness.v ,vpi_user.cc files

• How can I test the Hello.v file?
• What is the usage of vpi_user.cc?

回答1:

To test your design in VCS you can use the two verilog files generated:

• Hello.v : Your Chisel design generated in Verilog
• Hello-harness.v : Your testbench code in Verilog (generated by --genHarness option). Of course you have to modify it to improve your test.

来源：https://stackoverflow.com/questions/31444699/how-to-test-the-verilog-module-generated-by-chisel-in-vcs-how-does-vpi-uer-cc