Altera FPGA时序约束set_false_path
A false path can be a path logically impossible. Let's take a circuit shown below as an example. As we can see from the diagram, it is logically impossible from a1, through f1 and b2, to f2. It also logically impossible from b2, through f1 and a2, to f2. In such cases, we can use PrimeTime command set_false_path to disable the timing paths.. set_false_path -through a1 -through b2 set_false_path -through b1 -through a2 A false path can also be a path cross asynchronous clock domains. Let's assuming clk1 is asynchronous to clk2, we can also disable the false paths like following. set_false_path