A false path can be a path logically impossible. Let's take a circuit shown below as an example.
As we can see from the diagram, it is logically impossible from a1, through f1 and b2, to f2. It also logically impossible from b2, through f1 and a2, to f2. In such cases, we can use PrimeTime command set_false_path to disable the timing paths..
set_false_path -through a1 -through b2
set_false_path -through b1 -through a2
A false path can also be a path cross asynchronous clock domains. Let's assuming clk1 is asynchronous to clk2, we can also disable the false paths like following.
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
set_false_path -from [get_clocks clk2] -to [get_clocks clk1]
Or we can use set_clock_group to do same thing.
set_clock_group -name asyn_clocks -asynchronous -group clk1 -group -clk2
1. Why we want to set false path?
Just We want to tell tools don't care about these special path, and we can make sure these defined path have no need to check or we have other methods to check , such as dynamic simulation for asynchrous path, or handshake function check for different clock domain.
2. Which path we should set as false path?
1). logic impossible path: we should specify these path which cannot exist in logic function, but tools cannot get enough info about these impossible path,especially multi master/slave bus commulation , mux selection function, memory R/W function.
2). CDC (clock domain constaint) :for these multi asynchrous clock domain, we can use handshake or FIFO to communicate.
3). test function logic path : for one real chip , we should have enough logic for scan test or BIST test, or JTAG test, we should seperate STA as scan test, function test, at-speed test and BIST test. So in each case, we should set different test mode enable ,and set other path as false path. For example, when we do function test, we should set scan and BIST data path as false path .
4) other specified path by designer
FALSE PATH
FPGA方面QuartusIIFALSE PATHFALSE PATH
QuartusIIFALSE PATH
1.
2.
1MUX_1MUX_2MUX_1CclkMUX_2CclkMUX_1S1MUX_2S1MUX_2DMUX_1S2MUX_2S2MUX_2DFALSE PATH
set_false_path
set_false_path
图1
2test_logicFALSE PATH
图2
set_false_pathto [get_pins test_logic|*|datain]
set_false_path
-to [get_pins test_logic|*|datain]
set_false_path
3reg1reg2clk1clk2FALSE PATH
set_false_pathto [get_pins reg2|datain]
图3
4clk_100clk_66FALSE PATH
set_false_path
set_false_path
FALSE PATH
set_clock_groups
图4