digital-logic

How does comparing the Sign and Overflow Flag determine operand relationships?

不问归期 提交于 2020-11-28 02:22:49
问题 Jump's based on comparing signed integers use the Zero, Sign, and Overflow flag to determine the relationship between operands. After CMP with two signed operands, there are three possible scenario's: ZF = 1 - Destination = Source SF = OF - Destination > Source SF != OF - Destination < Source I'm having trouble understanding scenario 2 and 3. I've worked through the possible combinations and see that they do work - but I still can't figure out why they work. Can anyone explain why a

How does comparing the Sign and Overflow Flag determine operand relationships?

你说的曾经没有我的故事 提交于 2020-11-28 02:21:27
问题 Jump's based on comparing signed integers use the Zero, Sign, and Overflow flag to determine the relationship between operands. After CMP with two signed operands, there are three possible scenario's: ZF = 1 - Destination = Source SF = OF - Destination > Source SF != OF - Destination < Source I'm having trouble understanding scenario 2 and 3. I've worked through the possible combinations and see that they do work - but I still can't figure out why they work. Can anyone explain why a

How does comparing the Sign and Overflow Flag determine operand relationships?

青春壹個敷衍的年華 提交于 2020-11-28 02:20:08
问题 Jump's based on comparing signed integers use the Zero, Sign, and Overflow flag to determine the relationship between operands. After CMP with two signed operands, there are three possible scenario's: ZF = 1 - Destination = Source SF = OF - Destination > Source SF != OF - Destination < Source I'm having trouble understanding scenario 2 and 3. I've worked through the possible combinations and see that they do work - but I still can't figure out why they work. Can anyone explain why a

How does comparing the Sign and Overflow Flag determine operand relationships?

喜你入骨 提交于 2020-11-28 02:19:27
问题 Jump's based on comparing signed integers use the Zero, Sign, and Overflow flag to determine the relationship between operands. After CMP with two signed operands, there are three possible scenario's: ZF = 1 - Destination = Source SF = OF - Destination > Source SF != OF - Destination < Source I'm having trouble understanding scenario 2 and 3. I've worked through the possible combinations and see that they do work - but I still can't figure out why they work. Can anyone explain why a

FSM for long bit sequence

不问归期 提交于 2020-03-25 22:00:27
问题 Currently, I'm working on a mealy fsm that detects a 17 bit sequence 10100001010000001. Due to the length of the sequence, I'm having difficulty figuring out which state to return to when the input doesn't allow me to move on to the next state. Any suggestions ?? 来源: https://stackoverflow.com/questions/60181822/fsm-for-long-bit-sequence

self completing code

怎甘沉沦 提交于 2020-01-24 00:38:06
问题 https://electronics.stackexchange.com/questions/20537/how-to-identify-self-complementing-code I have read that properly , but is it necessary that , the number need to be subtracted from 9 ? because in the 8421 system 12= 1100 and if we subtract 15-12 , then the answer is 3 , which is 0011 . so it is also self complementing... I don't understand that , the given number need to be subtracted from which number , is that number neccessary to be 9 ??? 回答1: If the sum of the weights is 9 then it

How is Carry Flag set when subtrahend is larger?

痞子三分冷 提交于 2019-12-24 00:15:43
问题 I know the Carry flag during SUB is set whenever the minuend is smaller than the subtrahend and a borrow is required, but haven't been able to find anything explaining this in more detail. Since subtraction is actually just adding with two's complement, how does the CPU know that the subtrahend is larger and a borrow has occurred? The only thing I can think of is that maybe the Carry flag is set automatically during SUB , whenever converting the subtrahend to its 2's complement. Then unless

How to handle loops in a digital logic simulator?

痞子三分冷 提交于 2019-12-23 09:22:40
问题 I'm developing a digital logic simulator to build my own CPU in it later (so it's a long term project). Everything works great for circuits with no loops, for example a fulladder. Then there are circuits like an SR latch, where one of the inputs of a gate is connected to the output of another gate. So I'm in a loop, because both gates need the output of the other one, to compute their own output. What is the best way to solve this? I implemented it in a way, that (when a loop is detected) it

Use of wire inside an always block?

落花浮王杯 提交于 2019-12-20 04:15:36
问题 Can I use a wire inside an always block? Like for example: wire [3:0]a; assign a=3; always @(c) begin d=a+c; end It got compiled without throwing any error. Why? 回答1: Yes, you can use a wire's value inside an always block, you just can not assign a value to a wire in always or initial block. The only real difference between a wire and reg is the syntax for assigning values. In the above example d could also have been created as a wire, these are equivalent: reg [3:0] answer_reg; always @*

Truth Table Generation

我与影子孤独终老i 提交于 2019-12-14 03:27:59
问题 Anybody have thoughts on generating a row of a truth table with out creating the entire table. For example, a user would enter in a row number and that truth table row is generated. Also, this should be done without creating the table until you get to that row number. Essentially, I want to know if there is an efficient way to calculate a truth row value only based on a the truth table row as an input. Example: Assume 3 variables printTruthTableRow(3) would produce 010 Actually, could I just