cpu-cache

While questions have been asked before about linked lists versus arrays, the answers mostly boil down to what most of us probably have already learned at some point: Lists are good at inserting and deleting Arrays are good at random access Now respectable people like Bjarne Stroustrup have argued that arrays practically always outperform linked lists because they make much better use of the caching architecture implemented in modern hardware. He also states that the performance advantage of arrays increases with their size. While I basically understand his arguments and agree with him, I

I am building a cache simulator for a intel core i7 but have a hard time finding the detailed specifications for the L1, L2 and L3 cache (shared). I need the Cacheblock size, cache size, associativity and so on... Can anyone point me in the good direction? Intel's Optimization guide describes most of the required specifications per architectural generation (you didn't specify which i7 you have, there are now several generations since Nehalem and up to Haswell). Haswell, for e.g., would have - Note that if you're building a simulator, you'll want to have as many of these feature as possible

I'm trying to figure out how to calculate the miss rate of an array. I have the answer, but I'm not understanding how the answer was arrived at. I have the following code: int C[N1][N2]; int A[N1][N3]; int B[N3][N2]; initialize_arrays(A, B, C, N1, N2, N3); for(i=0; i<N1; ++i) for(j=0; j<N2; ++j) for(k=0; k<N3, ++k) C[i][j] += A[i][k] * B[k][j]; I also have the following info: N1=N2=N3=2048 (what does this mean??). The processor has an L1 data cache of 32kB with line size of 64B (no L2 cache). (what is line size?) I know the miss rate of array C is (N^2/16)/N^3 . I know the formula is (total

I found a way to read L1(data and instruction) cache using http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka4237.html . I want to read L2 performance counters too. Is there anyone who knows how to measure L2 cache hit rate possibly with ARM assembly or in higher level like Java? Accessing performance data for the L2 is dependent on the L2-controller. I don't know how many different ones there are, but for current A9 platforms the PL310 is pretty common and features event counters which can capture requests and hits (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc

I have been running some benchmarks on some algorithms and profiling their memory usage and efficiency (L1/L2/TLB accesses and misses), and some of the results are quite intriguing for me. Considering an inclusive cache hierarchy (L1 and L2 caches), shouldn't the number of L1 cache misses coincide with the number of L2 cache accesses ? One of the explanations I find would be TLB related: when a virtual address is not mapped in TLB, the system automatically skips searches in some cache levels. Does this seem legitimate? First, inclusive cache hierarchies may not be so common as you assume. For

When my program performs a load operation with acquire semantics/store operation with release semantics or perhaps a full-fence, it invalidates the CPU's cache. My question is this: which part of the cache is actually invalidated? only the cache-line that held the variable that I've used acquire/release? or perhaps the entire cache is invalidated? (L1 + L2 + L3 .. and so on?). Is there a difference in this subject when I use acquire/release semantics, or when i use a full-fence? I'm not an expert on this, but I stumbled on this document, maybe it's helpful http://www.rdrop.com/users/paulmck