I found a way to read L1(data and instruction) cache using http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka4237.html. I want to read L2 performance counters too. Is there anyone who knows how to measure L2 cache hit rate possibly with ARM assembly or in higher level like Java?
Accessing performance data for the L2 is dependent on the L2-controller. I don't know how many different ones there are, but for current A9 platforms the PL310 is pretty common and features event counters which can capture requests and hits (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246a/index.html ). Though accessing those counters might be difficult. If you're lucky the kernel might offer an interface to those registers, but it's likely that not and that they aren't accessible from user space. In that case you would have to find the memory map for your platform and write a kernel module or something like that.
来源：https://stackoverflow.com/questions/5509630/how-to-read-l2-cache-hit-miss-rate-in-android-arm