cpu-architecture

问题 Here is the code sample var startInfo = new ProcessStartInfo { Arguments = commandStr, FileName = @"C:\Windows\SysWOW64\logman.exe", }; using (var createCounterProc = new Process { StartInfo = startInfo }) { createCounterProc.Start(); createCounterProc.WaitForExit(); } After running the code I get "A 32 bit processes cannot access modules of a 64 bit process." message in MainModule (NativeErrorCode:299). My solution is configured to AnyCPU. I've tried both 64 and 32 bit versions of logman.exe

问题 I have been reading about the four ways a cache can be addressed: Physically Indexed Physically Tagged (PIPT) Physically Indexed Virtually Tagged (PIVT) Virtually Indexed Physically Tagged (VIPT) Virtually Indexed Virtually Tagged (VIVT) Which of the following caches would suffer from the synonym and homonym issues? I know that the VIVT would suffer from these issues and PIPT won't. But what about PIVT and VIPT? 回答1: Since synonyms occur when different virtual addresses map to the same

问题 I'd like to ask why the BLT instruction is not a part of MIPS ISA. Instead they actually make it a pseudo-instruction for assembly programmers. I just couldn't recognize the difference between BLT and BLTZ (which is a part of MIPS ISA) from hardware implementation point of view. By the way the book "Computer Organization and Design" says : Heeding von Neumann's warning about the simplicity of the "equipment" the MIPS architecture doesn't include branch on less than because it's too

问题 I'd like to ask why the BLT instruction is not a part of MIPS ISA. Instead they actually make it a pseudo-instruction for assembly programmers. I just couldn't recognize the difference between BLT and BLTZ (which is a part of MIPS ISA) from hardware implementation point of view. By the way the book "Computer Organization and Design" says : Heeding von Neumann's warning about the simplicity of the "equipment" the MIPS architecture doesn't include branch on less than because it's too

问题 This question already has answers here : Does each core has its own private set of registers? (2 answers) What does multicore assembly language look like? (10 answers) Why each logical CPU has it's own CR3 register in case of multithreading? (1 answer) Can I temporarily enable FTZ and DAZ floating-point modes for a thread? (1 answer) Closed last year . I'm trying to read the Intel documentation on the CPU registers, and the question came up that I can't seem to find an answer to. Say, all of

问题 When an interrupt comes to CPU, it is handled by saving current address location prior jumping into the handler if it is acknowledged. Otherwise it is ignored. I wonder whether an assembly instruction call is interrupted. For example, mvi a, 03h ; put 3 value into acc. in 8080 assembly Can be the one line instruction interrupted? Or if not, it is atomic?? Is there always a guarantee that "one line assembly instruction" is always atomic?? What if there is no "lock" keyword i.e. in 8080

问题 I'm doing an experiment and the first step is to unroll a loop (from C/C++) a dozen of times (ex: 10, 50, etc) and output the C/C++ unrolled code. Is there any tool that I can use to automatize such unrolling? In other words, what I need is: C/C++ source/loop --->> TOOL (Unroll by X) ----> Unrolled C/C++ source/loop 回答1: Our source-to-source transformation engine, the DMS Software Reengineering Toolkit, with its C++17 front end can be used to do this. DMS can accept explicit source-to-source

问题 Is there any documentation on this? I'm trying to get a handle on the feasibility of writing a compiler for the Tilera architecture. 回答1: The source code of their gcc compiler at www.tilera.com/scm includes gcc-style machine description (.md) files that define the instructions and other micro-architectural details needed by a compiler writer. 回答2: Rephrasing this answer, for clarity. Many references on the web claim they're supposedly MIPS derivates; on the other hand, neither has MIPS' own

问题 Is there any documentation on this? I'm trying to get a handle on the feasibility of writing a compiler for the Tilera architecture. 回答1: The source code of their gcc compiler at www.tilera.com/scm includes gcc-style machine description (.md) files that define the instructions and other micro-architectural details needed by a compiler writer. 回答2: Rephrasing this answer, for clarity. Many references on the web claim they're supposedly MIPS derivates; on the other hand, neither has MIPS' own

问题 Under the total store order(TSO) memory consistency model, a x86 cpu will have a write buffer to buffer write requests and can serve reordered read requests from the write buffer. And it says that the write requests in the write buffer will exit and be issued toward cache hierarchy in FIFO order, which is the same as program order. I am curious about: To serve the write requests issued from the write buffer, does L1 cache controller handle the write requests, finish the cache coherence of the