cpu-architecture

问题 I want to add some third party libraries to Contiki, but at the moment I can't. So I wanted to just test with a simple library. I wrote two files hello.c hello.h, in hello.c I have: printf(" Hello everbody, library call\n"); In hello.h I have: extern void print_hello(); I created hello.o using the command: msp430-gcc -mmcu=msp430f1611 hello.c -o hello.o I created an archive file: ar -cvq libhello.a hello.o I move to contiki, i write a simple program that calls hello.h to execute a function.I

问题 I'm reading the book The RISC-V Reader: An Open Architecture Atlas . The authors, to explain the isolation of an ISA ( Instruction Set Architecture ) from a particular implementation (i.e., microarchitecture) wrote: The temptation for an architect is to include instructions in an ISA that helps performance or cost of one implementation at a particular time, but burden different or future implementations. As far as I understand, it states that when designing an ISA, the ISA should ideally

问题 Does GPGPU programming only allow the execution of SIMD instructions? If so then it must be a tedious task to re write an algorithm that has been designed to run on a general CPU to run on a GPU? Also is there a pattern in algorithms that can be converted to SIMD architecture? 回答1: Well, it's not quite exact that GPGPU only supports SIMD execution. Many GPUs have some non-SIMD components. But, overall, to take full advantage of a GPU you need to be running SIMD code. However, you are NOT

问题 While going through computer Architecture, I learnt different method of controlling I/O device which are, Programmed I/O Interrupt I/O DMA I learnt all three methods. But I come across another term Memory Mapped I/O . Is there any relation between Programmed I/O and Memory Mapped I/O ? I am confused with these two. Are they similar? 回答1: Those terms are mostly independent and not mutually exclusive. Below I'll use a pseudo-assembly code to make the examples clearer, it is a demonstrative code

问题 I am reading about different prefetcher available in Intel Core i7 system. I have performed experiments to understand when these prefetchers are invoked. These are my findings L1 IP prefetchers starts prefetching after 3 cache misses. It only prefetch on cache hit. L2 Adjacent line prefetcher starts prefetching after 1st cache miss and prefetch on cache miss. L2 H/W (stride) prefetcher starts prefetching after 1st cache miss and prefetch on cache hit. I am not able to understand the behavior

问题 Does anyone know which type of CPU cache behaviour or policy (e.g. uncacheable write-combining) is assigned to memory mapped file-backed regions on modern x86 systems? Is there any way to detect which is the case, and possibly override the default behaviour? Windows and Linux are the main operating systems of interest. (Editor's note: the question was previously phrased as memory mapped I/O, but that phrase has a different specific technical meaning, especially when talking about CPU caches.

问题 Due to the huge impact on performance, I never wonder if my current day desktop CPU has branch prediction. Of course it does. But how about the various ARM offerings? Does iPhone or android phones have branch prediction? The older Nintendo DS? How about PowerPC based Wii? PS 3? Whether they have a complex prediction unit is not so important, but if they have at least some dynamic prediction, and whether they do some execution of instructions following an expected branch. What is the cutoff

问题 Say we have a certain parent process with some arbitrary amount of data stored in memory and we use fork to spawn a child process. I understand that in order for the OS to perform copy on write, the certain page in memory that contains the data that we are modifying will have its Read-only bit set, and the OS will use the exception that will result when the child tries to modify the data to copy the entire page into another area in memory so that the child gets it's own copy. What I don't

问题 Consider the diagrammed data cache architecture. (ASCII art follows.) -------------------------------------- | CPU core A | CPU core B | | |------------|------------| Devices | | Cache A1 | Cache B1 | with DMA | |-------------------------| | | Cache 2 | | |------------------------------------| | RAM | -------------------------------------- Suppose that an object is shadowed on a dirty line of Cache A1, an older version of the same object is shadowed on a clean line of Cache 2, and the newest

问题 It is my understanding that ARMv7 processors, such as the Cortex-A9, are mostly backwards-compatible with code for older ARM architecture versions. However, I've read reports of segfaults trying to run ARM9 code on a Cortex-A8, for example. What parts of ARMv4/5/6 (ARM7TDMI/ARM9/ARM11) code will not work on an ARMv7 processor? What features or architectural characteristics exist in these older ARM architecture versions that can cause a program built for these versions to fail on ARMv7? 回答1: