cpu-architecture

问题 In the general case, how can an instruction that can take memory or register operands ever be slower with memory operands then mov + mov -> instruction -> mov + mov Based on the throughput and latency found in Agner Fog's instruction tables (looking at Skylake in my case, p238) I see that the following numbers for the btr/bts instructions: instruction, operands, uops fused domain, uops unfused domain, latency, throughput mov r,r 1 1 0-1 .25 mov m,r 1 2 2 1 mov r,m 1 1 2 .5 ... bts/btr r,r 1 1

问题 Does cache memory refresh itself if doesn't encounter any instruction for a threshold amount of time? What I mean is that suppose, I have a multi-core machine and I have isolated core on it. Now, for one of the cores, there was no activity for say a few seconds. In this case, will the last instructions from the instruction cache be flushed after a certain amount of time has passed? I understand this can be architecture dependent but I am looking for general pointers on the concept. 回答1: If a

问题 I am studying about cache effect using a simple micro-benchmark. I think that if N is bigger than cache size, then cache have a miss operation every first reading cache line. In my machine, cache line size=64Byte, so I think totally cache occur N/8 miss operation and cache grind show that. However, perf tool displays different result. It only occur 34,265 cache miss operations. I am doubted about hardware prefetch, so turn off this function in BIOS. anyway, result is same. I really don't know

问题 My understanding currently is, I can write an operating system in C I can write a program for that operating system in C When I write an operating system I can see all of the memory When I write a program the operating system hides memory from other programs from me. Whenever a program runs inside an OS it appears to the program as if the memory it is allocated is all the memory the computer has How does the CPU / OS achieve this? Is this something purely implemented on the software level? Or

问题 My understanding currently is, I can write an operating system in C I can write a program for that operating system in C When I write an operating system I can see all of the memory When I write a program the operating system hides memory from other programs from me. Whenever a program runs inside an OS it appears to the program as if the memory it is allocated is all the memory the computer has How does the CPU / OS achieve this? Is this something purely implemented on the software level? Or

问题 My understanding currently is, I can write an operating system in C I can write a program for that operating system in C When I write an operating system I can see all of the memory When I write a program the operating system hides memory from other programs from me. Whenever a program runs inside an OS it appears to the program as if the memory it is allocated is all the memory the computer has How does the CPU / OS achieve this? Is this something purely implemented on the software level? Or

问题 My understanding currently is, I can write an operating system in C I can write a program for that operating system in C When I write an operating system I can see all of the memory When I write a program the operating system hides memory from other programs from me. Whenever a program runs inside an OS it appears to the program as if the memory it is allocated is all the memory the computer has How does the CPU / OS achieve this? Is this something purely implemented on the software level? Or

问题 I'm thinking about how to negate a signed-integer in mips32. My intuition is using definition of 2's complement like: (suppose $s0 is the number to be negated) nor $t0, $s0, $s0 ; 1's complement addiu $t0, $t0, 1 ; 2's = 1's + 1 then I realized that it can be done like: sub $t0, $zero, $s0 so... what's the difference? Which is faster? IIRC sub will try to detect overflow, but would this make is slower? Finally, is there any other way to do so? 回答1: subu $t0, $zero, $s0 is the best way, and is

问题 Let's assume that variable a = 0 Processor1: a = 1 Processor2: print(a) Processor1 executes it's instruction first then in next cycle processor2 reads variable to print it. So is: processor2 gonna stall until cache coherence operation completes and it will print 1 P1: |--a=1--|---cache--coherence---|---------------- P2: ------|stalls due to coherence-|--print(a=1)---| time: -----------------------------------------------> processor2 will operate before cache coherence operation completes and

问题 I'm trying to understand the VEX prefix encoding for the SSE/AVX instructions. So please bear with me if I ask something simple. I have the following related questions. Let's take the MOVUP(D/S) instruction ( 0F 10 ). If I follow the 2-byte VEX prefix encoding correctly: The following two instruction encodings produce the same result: db 0fh, 10h, 00000000b ; movups xmm0,xmmword ptr [rax] db 0c5h, 11111000b, 10h, 00000000b ; vmovups xmm0,xmmword ptr [rax] As these two: db 066h, 0fh, 10h,