cpu-architecture

问题 The term Von Neumann languages is applied to programming languages whose computational model is based on the Von Neumann computer architecture. Is C++ considered a Von Neumann language, or if it's not (e.g., because of asynchronous execution with the advent of threads) was it ever considered a Von Neumann language? Is there an architecture that C++'s computational model/abstract machine is based on and thus can be classified as a language of that architecture? 回答1: TL:DR: The C++ abstract

问题 First of all, I don't think this question is a duplicate of Detect 64bit OS (windows) in Python because imho it has not been thoroughly answered. The only approaching answer is: Use sys.getwindowsversion() or the existence of PROGRAMFILES(X86) ( if 'PROGRAMFILES(X86)' in os.environ ) But: Does the windows environment variable PROGRAMFILES(X86) reliable? I fear that anyone can create it, even if it's not present on the system. How to use sys.getwindowsversion() in order to get the architecture

问题 First of all, I don't think this question is a duplicate of Detect 64bit OS (windows) in Python because imho it has not been thoroughly answered. The only approaching answer is: Use sys.getwindowsversion() or the existence of PROGRAMFILES(X86) ( if 'PROGRAMFILES(X86)' in os.environ ) But: Does the windows environment variable PROGRAMFILES(X86) reliable? I fear that anyone can create it, even if it's not present on the system. How to use sys.getwindowsversion() in order to get the architecture

问题 Closed. This question does not meet Stack Overflow guidelines. It is not currently accepting answers. Want to improve this question? Update the question so it's on-topic for Stack Overflow. Closed 4 months ago . Improve this question I'm trying to understand how PCI segment(domain) is related to multiple Host Bridges? Some people say multiple PCI domains corresponds to multiple Host Bridges, but some say it means multiple Root Bridges under a single Host Bridge. I'm confused and I don't find

问题 Closed. This question does not meet Stack Overflow guidelines. It is not currently accepting answers. Want to improve this question? Update the question so it's on-topic for Stack Overflow. Closed 4 months ago . Improve this question I'm trying to understand how PCI segment(domain) is related to multiple Host Bridges? Some people say multiple PCI domains corresponds to multiple Host Bridges, but some say it means multiple Root Bridges under a single Host Bridge. I'm confused and I don't find

问题 I find that during TLB missing process, some architecture use hardware to handle it while some use the OS. But when it comes to page fault, most of them use the OS instead of hardware. I tried to find the answer but didn't find any article explains why. Could anyone help with this? Thanks. 回答1: If the hardware could handle it on its own, it wouldn't need to fault. The whole point is that the OS hasn't wired the page into the hardware page tables, e.g. because it's not actually in memory at

问题 I find that during TLB missing process, some architecture use hardware to handle it while some use the OS. But when it comes to page fault, most of them use the OS instead of hardware. I tried to find the answer but didn't find any article explains why. Could anyone help with this? Thanks. 回答1: If the hardware could handle it on its own, it wouldn't need to fault. The whole point is that the OS hasn't wired the page into the hardware page tables, e.g. because it's not actually in memory at

问题 I had read that when CPU read from memory, it will read word size of memory at once (like 4 bytes or 8 bytes). How can CPU achieve something like: mov BYTE PTR [rbp-20], al where it copies only one byte of data from al to the stack. (given the data bus width is like 64 bit wide) Will be great if anyone can provide information on how it's implemented on the hardware level. And also, as we all know that when CPU execute program, it has program counter or instruction pointer that points to the

问题 I'm just checking to make sure I have a proper understanding of how memory access works. Say I have a word-addressable memory system with 64-bit words. How much memory could be accessed using a 32-bit address size? A 64 bit word is 8 bytes, so we're dealing with an 8 byte word. An 8 byte word can hold up to 2^8 (256). Given that we have a 32 bit address, we have 2^32, but since each word is taking up 256 of those, (2^32)/256 = 1677216 bytes. To put that into metric terms, we have 2^24 = (2^4)

问题 So I am learning how x86 works and have come across people saying that it is byte-addressable, yet can read words, double words, etc. How does the processor decide which method to use and when? E.g. for accessing the next instruction and when a user wants to read/write to memory, which addressing mode is used? 回答1: Every memory access has an operand-size specified by the machine-code instruction. (Addressing mode isn't the right term: different addressing modes are different ways of