【verilog】verilog实现串口传输UART
1.接收模块 代码: //****************uart receive module******************// //********************************************************// `define SIM module uart_rx#( parameter DATAWIDTH = 8, parameter BAUD_CNT_WIDTH = 12, parameter BIT_CNT_WIDTH = 4 ) ( input CLK, input RSTn, input rs232_rx,//input data output reg [ DATAWIDTH - 1 : 0 ] rx_data,//receive data output reg po_flag //finish sig ); `ifndef SIM localparam BAUD_END = 5207;//simulate time too long,change to 56(560) `else localparam BAUD_END = 56; `endif localparam BAUD_M = BAUD_END / 2 - 1; localparam BIT_END = 8; reg rx_r1; reg rx_r2; reg rx