assembly

问题 I have an RPi4 and I'm trying to write some code in assembly to loop 1000 times. The code works fine when I set a lower number of loops, but when I try to set it 1001, gcc says: loop.s: Assembler messages: loop.s:15: Error: invalid constant (3e9) after fixup Here's the code: .data ms3: .asciz "%d\n" .text .global main .extern printf main: push {ip, lr} mov r1, #0 mov r5, #1001 loop1000: push {r1} ldr r0, =ms3 bl printf pop {r1} add r1, #1 cmp r1, r5 bne loop1000 pop {ip, pc} 回答1: Assembly

问题 I am relatively inexperienced with ARM assembly, and need help understanding a few lines. I have used Godbolt to compile C++ 11 code with the ARM gcc 8.2 compiler and got these lines of assembly: .L10: .word .LANCHOR0 I read that .LANCHOR0 are section anchors, but what does that mean? I understand that .word and .data can be used together to declare variables and assign values to memory spaces like this: .data ! start a group of variable declarations x: .word 23 ! int x = 23; But, what does

问题 I have this assembly program where I need to find the substring in the main string I input. My problem is that it always outputs the "word found" even if I typed two completely different words. I don't know which part of my loop or condition is wrong. Please help me figure it out. Also, please suggest some string instructions that could be used in checking for a substring so that I can shorten my code. I am really confused with how the cmpsb works, I only tried to use it. Btw, I don't know

问题 The op code portion of many important x86 instructions like MOV and ADD has the last two bits standardized as a direction bit and a data size bit: Is there any pattern to the part of the op code shown in gray here? For example, for ADD some of the instructions use the code 000000 and others have code 100000. 来源： https://stackoverflow.com/questions/41720529/is-there-a-pattern-to-x86-op-codes-other-than-direction-and-size-bits

问题 In MIPS, a 32-bit jump instruction consists of 6-bits for the opcode and 26-bits for the target (destination) address that we want to set the program counter to. However, it is possible to set the program counter to a 28-bit target address. How is this possible if we can only fit 26-bits in the jump instruction? 回答1: Instructions on MIPS are always 4-byte aligned, so the low 2 bits of any valid target address can only be zero. Thus, the 26 bits specified in jump instructions are always

问题 I've searched all over the web, but I couldn't find what the "fh" means in the following instruction and eax, 38fh . I know that "h" stands for hexadecimal and "d" for decimal, but I've never seen fh before. 回答1: If an Intel assembler (ie. MASM ) token starts with a number (0 to 9) then it is assumed to be that the entire token is a value. If the value ends with an h the assembler assumes it is H exadecimal. In your case 38fh starts with a number so it is assumed to be a value. The end of the

问题 The add instruction documentation from this page says the following: Notice the two instructions that I highlighted. I tried the following code in NASM (which conforms with the first highlighted instruction): add WORD [myvar], BYTE 0xA5 But I got the following error: warning: signed byte value exceeds bounds What am I doing wrong? 回答1: The 8-bit immediate operand (denoted here by imm8 ) is sign-extended into 16 (or 32) bits to match the size of the other operand ( r/m16 or r/m32 ,

问题 I am currently trying to compile and run a simple bootloader in bochs. Currently, this is my bootloader.asm file: [BITS 16] [ORG 0x7C00] ;Where the code gets mapped top: jmp top ;Loop forever times 510-($-$$) db 0 ;Pad with 0 dw 0xAA55 ;Bootloader signature (backwards) ;; dw declares a word (2 bytes because we’re 16 bits) From my pragmalinux-img directory I then type in the following commands: yasm bootloader.asm dd if=bootloader bs=512 bochs Upon running bochs I get the following error

问题 I had this question on my exam and i am confused because as far as i know that move $t0, $a0 # COPY $A0 TO $T0 in MIPS instruction provides that and MIPS is a RISC processor. Am I missing something? 回答1: Move is a pseudoinstruction, and when assembled will really be a different instruction. For instance move $t0, $zero gets implemented as addu $t0, $zero, $zero 来源： https://stackoverflow.com/questions/53286335/why-the-risc-instruction-sets-usually-do-not-contain-register-to-register-copy-i

问题 I'm in a gdb session to analyze a postmortem crash. I'm looking at disassemble output for a function and I see this: => 0x00007f8d354aed52 <+50>: callq *(%rax) The => indicates that this was the instruction called at the time of the crash. So I got a seg fault calling the function at *(%rax) . I'm pretty new to assembly. I see that parens around a register mean to deference (get the value at) that address. Thus (%rax) means to get the value of the pointer currently stored in %rax . What does