Altera Quartus Error (12007): Top-level design entity “alt_ex_1” is undefined

匿名 (未验证) 提交于 2019-12-03 01:48:02

问题:

I've looked at all the previous questions and no one seems to have a problem as simple as mine. Also I've searched the web and can't find a solution.

I'm new to VHDL and am trying to compile the simple example provided by Altera, which is as follows:

library ieee; use ieee.std_logic_1164.all;  entity light is port(x1, x2: in std_logic;           f: out std_logic); end light;  architecture LogicFunction of light is begin     f 

I followed the project creation steps in the Altera tutorial, but when I try to compile the project I get the error:

Error (12007): Top-level design entity "alt_ex_1" is undefined 

回答1:

In chapter Starting a New Project, you were asked to call your project light. It seems to me that you didn't follow that step correctly and name your project alt_ex_1. That's why you're getting 12007 error, since the compiler has no idea what is the top-level entity in you design.

To solve that problem you can:

  1. Change the top-level entity assignment in Assignments -> Device -> General.
  2. Set your module as top-entity via Project Navigator (Files -> Set as top-level entity).

Btw 1, 2, 3, ... - all about the same problem.



回答2:

My problem was about verilog code compiler. But when I search for problem, I always saw this question. So I decided to add my solution too to guide others. It took me much time to find solution. here is what I had done to solve the problem.Just follow these steps (Quartus II 14.0.0) ; Assignments -> Settings -> Top-Level Entity ->Select your module



回答3:

Just put the pointer over the file name in the project navigator panel and click with right button and then push on (set as top-level entity). Done.



标签
易学教程内所有资源均来自网络或用户发布的内容,如有违反法律规定的内容欢迎反馈
该文章没有解决你所遇到的问题?点击提问,说说你的问题,让更多的人一起探讨吧!