vhdl

问题 I have an issue with self implemented UART in VHDL. I wrote VHDL code which generates proper waveform when running on Altera ModelSim: UART.vhd: LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.ALL; entity UART is port ( clk_10mhz: in STD_LOGIC; uart_clk: out STD_LOGIC; txPin: out STD_LOGIC ); end entity; architecture Test of UART is signal txStart: STD_LOGIC := '0'; signal txIdle: STD_LOGIC; signal txData: STD_LOGIC_VECTOR(7 downto 0); component TX is port ( clk_in: in STD

问题 I'm currently writing a test bench for a VHDL design I made and I need to write a message to a text file. The message is of the format [instance_name];[simulation_time] (i.e. U0;700 ns ) and the filename must be [instance_name].log . Getting the instance name and simulation time is no problem, but writing to a custom filename has been problematic. Under simulation, the instance name will be given in the format: "U0\ComponentX\test\" and I would like to replace the slashes with underscores. Is

问题 I synthesized my design with Xilinx ISE 13.1. Target device is Virtex 5. Then I encountered this warning: WARNING:Xst:819 - "F:/FRONT-END/h264/inter/src/eei/eei_mvd.vhd" line 539: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <mvd_l0<3

问题 I am near to end in my project but stuck at some point. I can not resolve the problem After deciding VHDL is having a hard time shifting indexes of arrays, I decided to change my shifter module. Now it is properly compiling and the RTL schematic seems true, but unfortunately I used a rather non-innovative way to shift the scancodes. I defined an 64bit std_logic_vector that can hold up to 8 scancodes, and then parsed the 4 MSBmost bytes of this vector, and directed them to seven segment

问题 Having a simple test bench like: entity tb is end entity; architecture syn of tb is signal show : boolean; begin show <= TRUE after 10 ns; end architecture; ModelSim GUI allows simulation and waveform viewing with a Tcl script in "all.do" with: vlib pit vcom -work pit tb.vhd vsim pit.tb add wave sim:/tb/show run 20 ns Where to do all.do in the ModelSim GUI console will make library, compile, load tb model, and show the waveform: How to make a similar simple Tcl script for a similar simulation

问题 Quite a simple one, but I am pulling my hair out and need some fresh eyes. The problem is detailed below, originally I had the issue with a much larger package containing multiple items so stripped everything back to basics and still can't work it out... thanks in advance g Simple code: ---------------------------------- -- LIBRARY_DECLARATIONS ---------------------------------- library STD; use STD.standard.all; ---------------------------------- library IEEE; use IEEE.std_logic_1164.all; --

问题 I have this VHDL code: entity Element is port( clk, D, E, F, G: in std_logic; Qout: out std_logic); end Element; architecture beh of Element is signal Qint: std_logic; begin process(...) variable sel: std_logic_vector(1 downto 0); begin if D='1' then Qint<= '0'; elsif E='1' then Qint<= '1'; elsif rising_edge(clk) then sel:=F&G; case sel is when "00"=> Qint<= not Qint; when "01"=> Qint<= not Qint; when "10"=> Qint<= '0'; when "11"=> Qint<= Qint; when others=> null; end case; end if; end

问题 I am trying to create a modular arithmetic operation in this case: x*y mod n As far as I have read the fastest way to do it is using the Montgomery multiplication, but I cant understand how that is actually done in other to implement it in hardware using VHDL. Has someone been able to do it or have any library that enables me to use it? 回答1: A basic shift and add modular multiplication can be found here as a part of this open cores project. Here's another project that is using the Montgomery

问题 Im beginner with VHDL. I wanna make a divider that divide clk in by 2 whitch is as output F and F divided by 2 should be E. It always when I want to compile the code show me this error: Error (10818): Can't infer register for "E" at clk200Hz.vhd(29) because it does not hold its value outside the clock edge Thanks for help frequency_divider: process (reset, clk_in) begin if (reset = '1') then F <= '0'; E <= '0'; counter <= 0; else if rising_edge(clk_in) then if (counter = 2) then F <= NOT(F);

问题 With VHDL '93 introducing direct instantiation, when would you actually use a component now when your entity is in VHDL? The following are the only time when a component is required I can think of: Component maps to non VHDL source (Verilog, netlist etc) You don't have the source yet and need something to compile against (eg. colleague hasn't finished their code yet) You are binding different entity/architecture pairs to specific components in specific entities via configs. (but who ever