vhdl

问题 Here is my dilemma: I'm very new to programming in VHDL, and I'm currently working on an independent study project for a university class. I've made some descent headway, but I've run into an issue I haven't been able to solve. What I'm trying to do is to display a "register" (or registers) on an LCD monitor and have it update periodically. For the time being, these values will always be integer numbers. I have code written which displays numbers properly on the screen if that value is passed

问题 Could some explain why i get syntax error with this piece of code.. An <= "1110" when anode = "00" else AN <= "1101" when anode = "01" else An <= "1011" when anode = "10" else An <= "0111" when anode = "11"; segment <= counter_1r when anode = "00" else segment <= counter_10r when anode = "01" else segment <= counter_100r when anode = "10" else segment <= counter_1000r When anode = "11"; it says ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 181. Type of An is incompatible with type

问题 I know this is a fairly notorious topic, but none of the usual solutions seem to be working.. Here's the line that's giving the error: ppl_stage_cnt <= ppl_stage_cnt + 1; Here's the error I get (from xst): Line 89: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+" Here's more information to put it in context: signal ppl_stage_cnt : std_logic_vector(log2(ppl)-1 downto 0); pplstage_cnt: process ( clk ) begin if rising_edge( clk ) then if rst =

问题 I am trying to implement a one bit counter using structural VHDL and components. I am getting a syntax error when trying to do the port map. The error is "Error (10028): Can't resolve multiple constant drivers for net "P" at Assign4.vhd(47)" Here is what I have so far: Thank you in advance for any ideas. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -------------------------------------------------------------- Entity Assign4 is Generic (bits: POSITIVE := 1);

问题 How to generate a PWM signal using an FPGA? Which is best method to generate a variable duty cycle? I tried to solve this problem by using the following code but two or three errors occurred. This is my code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; --use ieee.float_pkg.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use

问题 I want to get an accurate power report that contains real dynamic and static power consumption. I'm working on Xilinx spartan3 board. My code has no errors but after selecting the "Generate Text Power Report" in ISE (Xilinx synthesis tool), always the power report shows that my design has no dynamic power consumption. (Why?) Power report : Dynamic = 0.00 Quiescent = 59.84 Total = 59.84 My code : LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY SRAM IS PORT( clk : IN std_logic; wr : IN std

问题 this my code for an accumulator: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity akkumulator is generic (N : natural:=1); port(rst: in bit; clk: in bit; B : in natural range 0 to N-1; A : out natural range 0 to N-1); end akkumulator; architecture verhalten of akkumulator is begin p1: process(rst, clk) variable ergebnis : natural range 0 to N-1; begin if (rst = '1') then ergebnis := 0; elseif (clk'event and clk = '1') then ergebnis := ergebnis + B; end if; A <=

问题 From the Aldec Active-HDL GUI the vlib should create a work library, e.g.: vlib my_lib This creates a "my_lib" directory under the current directory, but with the warning: Warning: Cannot create library A subsequent set worklib my_lib fails with error "Error: Design not loaded.", and a compile with vcom -work my_lib tb.vhd completes without output and neither compiles anything to the "my_lib" directory. So it looks like even through a "my_lib" directory is created, it is not made available as

问题 This really shouldn't be this difficult. I want to read raw 64-bit IEEE 754 double-precision floating-point data from a file, and use it in a std_logic_vector(63 downto 0) . I'm using ModelSim ALTERA 10.1b. I tried to just read the raw binary data into the 64-bit vector: type double_file is file of std_logic_vector(63 downto 0); file infile1: double_file open read_mode is "input1.bin"; variable input1 : std_logic_vector(63 downto 0) := (others => '0'); read(infile1, input1); But this doesn't

问题 I want to implement the K&R algorithm for hamming weight calculation of 256 bit vector. I have written my code in vhdl as: entity counter_loop is Port ( dataIn : in STD_LOGIC_VECTOR (255 downto 0); dataOut : out STD_LOGIC_VECTOR (8 downto 0); threshold : in STD_LOGIC_VECTOR (8 downto 0); clk : in STD_LOGIC; flag : out STD_LOGIC); end counter_loop; architecture Behavioral of counter_loop is signal val : STD_LOGIC_VECTOR (255 downto 0) := X