Addition in VHDL not compiling?

问题

I know this is a fairly notorious topic, but none of the usual solutions seem to be working..

Here's the line that's giving the error:

ppl_stage_cnt <= ppl_stage_cnt + 1;

Here's the error I get (from xst):

Line 89: found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"

Here's more information to put it in context:

signal ppl_stage_cnt : std_logic_vector(log2(ppl)-1 downto 0);


pplstage_cnt: process ( clk )
begin
    if rising_edge( clk ) then      
        if rst = '1' or ei = '1' or li = '1' then
            ppl_stage_cnt <= (others => '0');
        else
            ppl_stage_cnt <= ppl_stage_cnt + 1;
        end if;
    end if;
end process;   

Other things I've tried:

ppl_stage_cnt <= std_logic_vector(to_unsigned(ppl_stage_cnt, log2(ppl)) + 1);

ppl_stage_cnt <= std_logic_vector(unsigned(ppl_stage_cnt) + '1');

回答1:

Try

ppl_stage_cnt <= UNSIGNED(ppl_stage_cnt) + 1;

source: http://objectmix.com/vhdl/190708-how-do-perform-std_logic_vector-addition-using-ieee-numeric_std.html, the second hit on google for std_logic_vector operator

来源：https://stackoverflow.com/questions/8109078/addition-in-vhdl-not-compiling