Minimal sensitivity list in VHDL

问题

I have this VHDL code:

  entity Element is port(
   clk, D, E, F, G: in std_logic;
   Qout: out std_logic);
   end Element;

   architecture beh of Element is
   signal Qint: std_logic;
   begin

    process(...)
       variable sel: std_logic_vector(1 downto 0);
    begin
       if D='1' then
          Qint<= '0';
       elsif E='1' then
          Qint<= '1';
       elsif rising_edge(clk) then
          sel:=F&G;
          case sel is
            when "00"=> Qint<= not Qint;
            when "01"=> Qint<= not Qint;
            when "10"=> Qint<= '0';
            when "11"=> Qint<= Qint;
            when others=> null;
          end case;
       end if;
    end process;

   Qout<= Qint;

   end beh;

My question is: Which of this signals I must write in sensitivity list if I want MINIMAL sensitivity list?

回答1:

You have to include in your sensitivity list all signals that are read and not inside a clocked part of your process.

You read D and E asynchronously. You read clk as part of your register. Therefore you have to include them.

process (D, E, clk)
begin
end process;

Notice: In VHDL-2008, the minimal sensitivity list is

process (all)
begin
end process;

EDIT: A bit more about the sensitivity list in general.

Simulation in VHDL is done in deterministic cycles. For every signal assignment all dependent signals will have to be updated as well, because that's what happens in hardware.

The simulator (e.g. modelsim, isim) will step through your HDL, determine all signal changes, then determine what other signals depend on these changes. The second set of changes is then simulated and another set of dependent signals is found and so on. The simulation goes on until a) a steady state is reached or b) a maximum number of iterations has passed.

Now, with a large design and the need to re-evaluate every process on every signal assignment, the complexity explodes. To prevent that, every process is only re-evaluated when a signal in its sensitivity list changes. Back in the day, software could not automatically detect all the signals it needed to listen to (or could ignore) for a given process, so the user had to give the tools a hint via the sensitivity list.

Nowadays, with VHDL-2008, software got so smart and CPUs got so fast, that simulation software can simply analyze all of the HDL and determine dependencies by itself.

Now, why is Qint not in the sensitivity list? Because changes in Qintdon't propagate to other signals until the next rising edge of clk. It is only sampled exactly at the edge of clk.

Therefore, Qint is only used in the clocked part of the process and by itself does determine the state of another signal.

And that's what you expect for a register. The input is sampled when the clock rises/falls and then stored and propagated to the output. In-between clock edges, the input signal can (and often will) change, but quickly settle to a valid logic state.

回答2:

Sigasi checks for incomplete sensitivity lists while you code. It also offers a Quick Fix to automatically add missing signals to the list. This way you do not have to worry about this yourself anymore.

来源：https://stackoverflow.com/questions/27949814/minimal-sensitivity-list-in-vhdl

标签

vhdl