What is the usefulness of a component declaration?

问题

With VHDL '93 introducing direct instantiation, when would you actually use a component now when your entity is in VHDL? The following are the only time when a component is required I can think of:

1. Component maps to non VHDL source (Verilog, netlist etc)
2. You don't have the source yet and need something to compile against (eg. colleague hasn't finished their code yet)
3. You are binding different entity/architecture pairs to specific components in specific entities via configs. (but who ever actually does this? maybe if you have a simulation arch and synth arch - but again - never seen it used in any meaningful way)

I am discounting people who preach that "A component lets me see the port map in the same file" or "having a component library allows me to see everything". This is mostly an old school approach that people have got into the habit of. In my eyes, maintaining the same code in two places makes no sense.

Are there any others Ive missed?

回答1:

Sorry for the late response to Can't compile VHDL package - Modelsim error: (vcom-1576) expecting END

In addition to the use case listed by the OP and in compliance with his criteria of not so useful cases, I'll add two more cases:

1. To write platform independent code, one needs to implement e.g. an Altera and a Xilinx specific solution. This code will reference vendor specific libraries like alter_mf or unisim. Both vendor specific implementations can be selected by a if ... generate-statement, or since VHDL-2008 by a case ... generate-statement.
   But even with generate-statements, this solution needs to instantiate components, because instances of a direct entity instantiation are bound regardless of the fact that some instances will never appear in the elaborated model. (I consider this a bug in the language - but there was no time to investigate and fix it for VHDL-2018.) Because an entity is immediately bound, the tool tries to load the referenced vendor library and it's packages.
   Let's assume you compile on Altera with Quartus, it will complain about an unknown unisim library and a unknown vcomponents package. The same happens on Xilinx with Vivado complaining about an unknown altera_mf library.
   Thus, to cut-off the (direct) instantiation tree, a component instantiation is needed.

   This technique is used by the PoC-Library. See for example the PoC.misc.sync.Bits implementation for a standard double-FF synchronizer with different attributes applied to an Altera, Xilinx or generic implementation.

2. In the Open Source VHDL Verification Methodology (OSVVM), components are used for two use cases:

   1. In a toplevel DUT, IP cores are instantiated as components so they can be replaced by dummy implementations. Either as unbound components or as components loading a dummy architecture. This can speed up simulations, reduce possible error sources in testing, replace complex slow implementations like MGTs or memory controllers with simpler and faster implementations, ...
   2. In OSVVM, the test control is implemented in a separate entity called TestController. This entity has several architectures to implement the different test cases applied to the same test hardness. The architectures are bound with a toplevel configuration per test case / architecture. Thus, running a "testbench" means elaborating and simulating one of these configurations.

来源：https://stackoverflow.com/questions/52806812/what-is-the-usefulness-of-a-component-declaration