vhdl

问题 I wrote some vivado RTL and then added some vhdl attributes to the ports of the entity to define the interface to Xilinx Vivado tool as follows: library ieee; use ieee.std_logic_1164.all; entity vivado_rtl_island is port( -- Clocks i_m50_clk :in std_logic; i_m50_rst :in std_logic; -- APB Command Inteface s_paddr :in std_logic_vector(31 downto 0); s_psel :in std_logic; s_penable :in std_logic; s_pwrite :in std_logic; s_pwdata :in std_logic_vector(31 downto 0); s_pready :out std_logic; s_prdata

问题 How do you zero-extend a fixed signal value? I have the following signal: signal shamt: std_logic_vector(4 downto 0); Before I assign it to another variable that is of size 31 downto 0 I have to zero extend shamt. I have the following code but I am unsure if it is correct. muxSOut <= conv_std_logic_vector(unsigned(shamt),32) when (muxSSel = '0') else A; I'm skeptical about the part conv_std_logic_vector(unsigned(shamt), 32). Will this extend shamt, which is of 5 bit size to 32 bit? So if

问题 I have the following architecture: architecture datapath of DE2_TOP is begin U1: entity work.lab1 port map ( --error on this line clock => clock_50, key => key, hex6 => hex6, hex5 => hex5, hex4 => hex4 ); end datapath; This architecture obviously depends on lab1 entity. Here is my lab1 entity and architecture: entity lab1 is port( clock : in std_logic; key : in std_logic_vector(3 downto 0); hex4, hex5, hex6 : out std_logic_vector(6 downto 0); value_counter : in unsigned(7 downto 0); register

问题 My question is regarding the first state used in a synthesized state machine. I'm working with a Lattice iCE40 FPGA, the EDA Playground for simulation and Lattice's Diamond Programmer for synthesizing. In the following example I am generating a series of signals (the example only shows the lines referring to the state machine). This works fine in simulation; i.e. the first case accessed is sm_init_lattice and the required signals are produced). However, the synthesized version goes straight

问题 I am new on VHDL, I have a push button which I want to detect the it signal when it is pushed, meaning i want to detect the raising edge of the signal push button when it is pressed? I did research and all what I found was about the detecting the raising edge of a clk. the problem that I have is that when the push button is pressed the the signal for the push button goes to 1 and stay at 1 until until another even happen so I am interested more when the signal of the push button raise? 回答1:

问题 I'm thinking about writing a C function which basically passes an array/vector of real numbers to a VHDL implementation as an argument and the VHDL code does some computation using the array in a FPGA and returns the result back to the C function. So, my question - How do I go about writing a C function to call the VHDL implementation? Can anyone guide me in the right direction like a tutorial,API or anything? Any help will be appreciated. Thanks! :) 回答1: VHDL does not result in a run time

问题 Please note that this question is not about how to change the code below to make it work; rather, I am looking for some insight on why a compiler would find this assignment ambiguous: entity assignment_to_aggregates is end; architecture example of assignment_to_aggregates is type vowel_type is (a, e, i, o, u); type consonant_type is (b, c, d, f, g); type vowel_consonant_pair is record vowel: vowel_type; consonant: consonant_type; end record; signal my_vowel: vowel_type; signal my_consonant:

问题 I have two processes A and B, each with its own clock input. The clock frequencies are a little different, and therefore not synchronized. Process A samples data from an IC, this data needs to be passed to process B, which then needs to write this data to another IC. My current solution is using some simple handshake signals between process A and B. The memory has been declared as distributed RAM (128Bytes as an array of std_logic_vector(7 downto 0)) inside process A (not block memory). I'm

问题 This question already has answers here : VHDL: Unable to read output status (2 answers) Closed last year . library IEEE; use IEEE.std_logic_1164.all; entity doorlock is port( reset : in std_logic; enable : in std_logic; password : in std_logic_vector (7 downto 0); door : out std_logic_vector (7 downto 0); lock : out std_logic; alarm : out std_logic; turnoff : out std_logic); end doorlock; --password is 10(decimal no.) which is 00010000(binary no.) architecture DDL of doorlock is signal err

问题 I'm using Xilinx ISE and generated a memory using the CORE Generator & Architecture Wizard. The problem is that it created a write enable signal ( wea ) as a STD_LOGIC_VECTOR(0 downto 0) and that results in a type mismatch: Line ###: Type error near encnt ; current type std_logic; expected type std_logic_vector How can I cast encnt , which is std_logic, to a one bit std_logic_vector? (ISE doesn't allow me to change wea from the file of memory.) 回答1: This is a pretty common scenario with these