vhdl

问题 I would like to set bits of a std_logic_vector separately in order to easily set comments for individual bits or group of bits. Here is what I have: signal DataOut : std_logic_vector(7 downto 0); ... DataOut <= ( 5=>'1', -- Instruction defined 4=>'1', -- Data length control bit, high=8bit bus mode selected 3=>'1', -- Display Line Number ctrl bit, high & N3 option pin to VDD=3 lines display 2=>'0', -- Double height font type control byte, not selected 1 downto 0=>"01", -- Select Instruction

问题 I am trying convert two std_logic bits to an integer as follows LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY TEST IS PORT (sw1, sw0 : IN std_logic; x : OUT integer RANGE 3 DOWNTO 0); END ENTITY TEST; ARCHITECTURE dflow OF TEST IS SIGNAL mes_sel : integer RANGE 3 DOWNTO 0; BEGIN mes_sel <= to_integer(unsigned(std_logic_vector(SW1 & SW0))); x <= mes_sel; END ARCHITECTURE dflow; but the compiler does not like the mes_sel assignment. I get the following compiler

问题 I was wondering if its possible to directly compare 2 vectors with eachother instead of just looking at them bit by bit. For example: entity Comparator is port(a,b in: std_logic_vector (2 downto 0); out1, out2 out: std_logic); end Comparator; architecture behavioural of Comparator1 is begin if a = b then out1 <= '1' else if /= then out2 <= '1' end if; end behaviour; Is this possible? 回答1: The answer is yes, you can compare two array types of the same type and subtype indication directly.

问题 I want to run a simulation in Quartus. So I assign a Testbench in the Assignment menu. My testbench includes my DUT(D) and a extra component(E), which is only for simulation (so this component includes statements which are not syntesizeable). My simulation runs if I remove E from my Testbench, but when I want to include E in my Testbench, I get the error from modelsim: my_testbench.vhd(197): (vcom-1195) cannot find expanded name "mylib.only_for_simulation". How could I make Quartus/Modelsim

问题 I want to run a simulation in Quartus. So I assign a Testbench in the Assignment menu. My testbench includes my DUT(D) and a extra component(E), which is only for simulation (so this component includes statements which are not syntesizeable). My simulation runs if I remove E from my Testbench, but when I want to include E in my Testbench, I get the error from modelsim: my_testbench.vhd(197): (vcom-1195) cannot find expanded name "mylib.only_for_simulation". How could I make Quartus/Modelsim

问题 I am quite new to Vivado and VHDL and I would like some guidance on a fundamental issue. I am guessing that I can create my own libraries and use them in my projects as i do with the default and fundamental ones eg: library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_unsigned.ALL; Now, by browsing on the net, I haven't found anything concrete as an answer, there is not any direct way to "add library" (at least in my version of Vivado). Is there any way to build VHDL code with lets

问题 I have the following simplified example of my code, where the DeltasTest entity can be simulated to show the issue. The clock in the real design is inverted or not based on a generic, and feeds several other entities below this one. The problem is that the simple edge detector does not work ( data_out is just a glitch) in behavioral simulation, due to the delta cycle delay introduced on the clock by the inversion stage. Is there a standard or otherwise elegant way to solve this? So far my

问题 How does one "include" another file from a workspace in VHDL and then use an architecure of an entity that is implemented in another file? Here is what I have but it is not right: updated code: library ieee; use ieee.std_logic_1164.all; library Part2; use Part2.all; entity problem4Gates is port(X,Clk: in std_logic; Q: out std_logic_vector(2 downto 0)) ; end entity problem4Gates; architecture behavioral OF problem4Gates IS for all: yourGateName use entity Part2.JKflipFlop(jkFF); --port (J, K,

问题 I am very new to VHDL and am trying to figure out how to do something fairly basic on an Altera Cyclone II. The FPGA has four push buttons - two of them need to be programmed to increase and decrease the selected register (0-F), and the two need to be programmed to increase and decrease the value (from 00 to FF) that will be in that register. Here is what I have so far: entity raminfr is port ( clk : in std_logic; we : in std_logic; a : in unsigned(3 downto 0); di : in unsigned(7 downto 0);

问题 I am very new to VHDL and am trying to figure out how to do something fairly basic on an Altera Cyclone II. The FPGA has four push buttons - two of them need to be programmed to increase and decrease the selected register (0-F), and the two need to be programmed to increase and decrease the value (from 00 to FF) that will be in that register. Here is what I have so far: entity raminfr is port ( clk : in std_logic; we : in std_logic; a : in unsigned(3 downto 0); di : in unsigned(7 downto 0);