VHDL std_logic_vector indexing with “downto”

问题

I would like to set bits of a std_logic_vector separately in order to easily set comments for individual bits or group of bits. Here is what I have:

signal DataOut : std_logic_vector(7 downto 0);
...
DataOut <= (                        5=>'1',     -- Instruction defined
                                    4=>'1',     -- Data length control bit, high=8bit bus mode selected
                                    3=>'1',     -- Display Line Number ctrl bit, high & N3 option pin to VDD=3 lines display
                                    2=>'0',     -- Double height font type control byte, not selected
                                    1 downto 0=>"01",   -- Select Instruction table1
                                    others=>'0' -- for bits 6,7
                                    );

However, I've a problem with the "downto" statement, I get the following error using Xilinx ISE:

Type std_ulogic does not match with a string litteral

Any solution to avoid using the equivalent

1=>'0',
0=>'1',

and to allow me to set bits by block?

回答1:

The assignment X downto Y => 'A' is correct when A is a element of array. For example, this snippet is correct:

1 downto 0 => '1',

And this snippet is wrong:

1 downto 0 => "01",

Therefore, your assignment is illegal. As your code, you can assign as:

DataOut <= (                        5 downto 3 =>'1',     
                                    2 downto 1 =>'0',     
                                    0 => '1',  
                                    others=>'0' 
                                    );

If you want to access/assign by a feild of array, you can use concatenation:

DataOut <= Something_0 & Something_1 & "01";

While Something_* is std_logic_vector

回答2:

Another answer is concatenation using '&', which loses the clarity of named association, though you can recover some of the self-documentation with named constants

constant Instr_Defined : std_ulogic := '1';
constant Bus_8_Bit     : std_ulogic := '1';

DataOut <= "00" & Instr_Defined
                & Bus_8_Bit
                & '1'     -- description
                & '0'     -- ditto
                & "01";

Another answer is to write a function to create instructions : this can make the main flow very simple and clear, while keeping the instruction encodings entirely separate and in a single place, e.g. in a package used wherever you need to know the instruction formats (perhaps in an assembler as well as the CPU)

DataOut <= Encode_Instruction(Instr_Defined, Bus_8_Bit, Font_Mode);

It's OK to use any of the preceding techniques, however verbose, in the function body. The more explicit and detailed the better; it isn't cluttering up the main design so you'll rarely look at it unless changing instruction formats.

回答3:

do this:

DataOut(7 downto 6)<="00";
DataOut(5)<='1';
DataOut(4)<='1';
DataOut(3)<='1';
DataOut(2)<='1';
DataOut(1 downto 0)<="01";

来源：https://stackoverflow.com/questions/15336875/vhdl-std-logic-vector-indexing-with-downto

标签

indexing

vhdl