system-verilog

问题 I know that if I am outputting a binary file in verilog, then I can use the following verilog IO standard function: $fwrite(fd,"%u",32'hABCDE124); But the above command writes 4-byte data into the file. What if the binary data that I want to write is only one-byte, two-bytes or three-bytes? How can I do this? For example, I know the following won't do what I want: $fwrite(fd,"%u",8'h24); $fwrite(fd,"%u",16'hE124); $fwrite(fd,"%u",24'hCDE124); Is there any way that I can write a non 4-byte

问题 Hi I am getting below error while compiling a c code using gcc /usr/lib/gcc/x86_64-redhat-linux/4.4.6/../../../../lib64/crt1.o: In function `_start': (.text+0x20): undefined reference to `main' collect2: ld returned 1 exit status I am trying to import the fftw() function into SystemVerilog. Here is my code #include <stdio.h> #include <stdlib.h> #include <stdint.h> #include <math.h> #include <fftw3.h> void fftw(double FFT_in[],int size) { double *IFFT_out; int i; fftw_complex *middle; fftw

问题 I am having trouble understanding why my code have a latch logic [1:0] lru_list [0:3]; always_comb begin if(reset) begin lru_list[0] = 0; lru_list[1] = 0; lru_list[2] = 0; lru_list[3] = 0; end else begin case({access, update, access_index_i < 4}) 3'b101: begin lru_list[0] = lru_list[0] + 1; lru_list[1] = lru_list[1] + 1; lru_list[2] = lru_list[2] + 1; lru_list[3] = lru_list[3] + 1; lru_list[access_index_i] = 0; end 3'b011: begin lru_list[0] = lru_list[0]; lru_list[1] = lru_list[1]; lru_list[2

问题 I have seen lots of system verilog program examples representing packets of data as a packed structure. Does this data travel serially like a packet? How does a system verilog structure be realized in hardware? 回答1: A packed structure in SystemVerilog simply gives you an alternative way to access fields of a signal by name instead of by bit position. For example typedef struct packed { logic [2:0] field1; // 3-bits logic [4:0] field2; // 5-bits } signal_t; // 8-bits You can now declare either

问题 I am learning system verilog and thought separate threads are created for each process in fork join. But I find if I have a while loop in my first process, my second process does not start which makes me think fork join is not actually parallel. class A; task run(); $display("A started"); while(1); endtask endclass class B; task run(); $display("B started"); endtask endclass Class C; task run(); fork A.run(); B.run(); join endtask endclass My output is Class A started and the program is

问题 Consider the following module declaration: module DFF(d, q, CLK, RESET); parameter W = 2; input [W-1:0] d; input CLK; input RESET; output logic [W-1:0] q; //.... endmodule What is the proper way of instantiating it where d and q are of enum type? Here is my enum type: typedef enum logic [1:0] {ENUM_IDLE = 0, ENUM_S1 , ENUM_S2 } T_STATE; I would like to instantiate the DFF for a T_STATE variable type: T_STATE d, q; DFF dff_inst (.d(d), .q(q), .CLK(CLK), .RESET(RESET)); This generates compile

问题 I sometimes use long assign statement in verilog which has nested if-else loop. Example assign a = (b) ? '1 : ((c&d) ? '0 : ((f&h) ? '1 : '0)); Another way to do this is to use an always_comb logic block. However the above approach saves time and easy to code up quickly. 回答1: Formatting There is nothing wrong with a nested conditional continuous assignment, but there are ways to make it more readable: assign a = (b) ? '1 : (c&d) ? '0 : (f&h) ? '1 : '0; However, this is still an "if...else if.

问题 can you say what is the meaning of that always @ * Is there any possible side effects after using that statement ? 回答1: It's just a shortcut for listing all of the wires that the always block depends on. Those wires are the "sensitivity list". One advantage of using it is that synthesized code is unlikely to care what you put in the sensitivity list (other than posedge and negedge ) because the wires will be "physically" connected together. A simulator might rely on the list to choose which

问题 In my Testbench, I have an interface that I need to drive. The interface can be driven in 2 different modes, with each mode having its own driver protocol and transaction type. So far, I have designed both uvm_agents separately. Now, I need a way to swap one or the other in, depending on the testcase I am running. I also want to do this in the way that best fits with UVM philosophy. My best method that I could come up with is: in my uvm_env, getting a uvm_db_config parameter from the test

问题 I want to have sth like this: generate for( i=0 ; i<16 ; i=i+1 ) begin: always @(posedge clk) begin L[i+1] <= #1 R[i]; R[i+1] <= #1 L[i] ^ out[i]; end end endgenerate I would appreciate it if any one could possibly help me. 回答1: You could do always @(posedge clk) begin L[16:1] <= #1 R[15:0] R[16:1] <= #1 L[15:0] ^ out; end 回答2: You don't need a generate here, I think. Just using a for loop within the always block will work. always @(posedge clk) begin for( int i=0 ; i<16 ; i=i+1 ) begin L[i+1