system-verilog

Get system time in VCS

由 ℡╲_俬逩灬. 提交于 2019-12-10 16:53:39
问题 Is there way to get system time in VCS/UVM ? I am looking for something similar to Perl's localtime(time) . Is there way to print system time for every uvm_info printed ? 回答1: One way is to use $system() to run any system command, including system' date command. initial begin $system("date"); end From IEEE 1800 LRM: $system makes a call to the C function system(). The C function executes the argument passed to it as if the argument was executed from the terminal. $system can be called as

how to get array of values as plusargs in systemverilog?

由 孤人 提交于 2019-12-10 16:42:53
问题 How to get the array of values as arguments in systemverilog, my requirement is I need get an array of commands of undefined size from the command line ,and how to get these arguments to an array/Queue Eg: +CMDS=READ,WRITE,READ_N_WRITE : It should be taken to an array ? 回答1: $value$plusargs does not support arrays, it does support strings. See IEEE Std 1800-2012 § 21.6 "Command line input". Parsing a string in SystemVerilog is only a little cumbersome but still very doable, especially when

Is recursive instantiation possible in Verilog?

由 倾然丶 夕夏残阳落幕 提交于 2019-12-10 16:38:53
问题 Some problems lead themselves to a recursive solution. Is recursive instantiation possible in Verilog? Is it possible for a module to instantiate itself? 回答1: Some problems lead themselves to a recursive solution. Finding the minimum of a set of numbers is just such a job: basically, the minimum of a set of numbers is the minimum of the minimum of the first half and the minimum of the second half. Take a set of numbers. Divide that set in half. Find the minimum of each half. The minimum of

what is the difference between automatic and static task,why we cant pass by reference to a static task

由 和自甴很熟 提交于 2019-12-10 15:06:46
问题 What is the difference between the static and automatic tasks. program class_ref; int index,value; class holding_values; int ass_array[*]; task assign_value (int value,int index); ass_array[index] = value; endtask function void disp(int index); $display("%t %M:ASSOSIATIVA VALUE%d ",$time,ass_array[index]); endfunction endclass initial begin holding_values obc; index =5; value =88; obc = new(); map(obc,value); obc.disp(index); end task map(ref holding_values obc,ref int value ); value +=5; obc

Modify verilog mode indentation

由 浪子不回头ぞ 提交于 2019-12-10 12:54:14
问题 I am trying to have verilog mode indent everything using 2 spaces except decls and always. This is what I added to my .emacs: ;; `define are not indented (setq verilog-indent-level-directive 0) ;; always, initial etc not indented (setq verilog-indent-level-module 0) ;; logic declarations are not indented (setq verilog-indent-level-declaration 0) ;;2 space indent (setq verilog-indent-level 2) ;; no indent on list and no indent when on multiple lines (setq verilog-indent-lists nil) (setq

forcing a bit in a wire system verilog

由 不羁的心 提交于 2019-12-10 12:12:59
问题 From testbench i have to corrupt a bus ins design. I am using a random variable to select a bit location (bit_sel) bit_sel = $urandom_range(0,MAX_LENGTH-1); Bus is somewhere deep inside the RTL with a width of MAXLENGTH. wire [MAX_LENGTH-1:0] BUS_TO_BE_FORCED; In TB is am using following line to corrupt the bus. force TOP.DUT.....BUS_TO_BE_FORCED[bit_sel] = ~TOP.DUT.....BUS_TO_BE_FORCED[bit_sel]; But i am getting compilation error. What is the best way to do this. I want to flip only one bit.

Verilog: Adding individual bits of a register (combinational logic, register width is parameterizable)

由 点点圈 提交于 2019-12-10 10:19:04
问题 I am trying to come up with a way to add individual bits of a register. eg, if regA = 111000 then regB = 3 (Sum of bits of regA ). 1) Is there any synthesizable function/operator in Verilog or SystemVerilog which I can directly use to do this operation? If not, then maybe the problem is a little interesting, especially because the operation has to be done in one clock cycle (pure combinational logic) and the register width is parameterizable. 2) In case there is no inbuilt Verilog or

Can Verilog/Systemverilog/VHDL be considered actor oriented programming languages?

由 二次信任 提交于 2019-12-09 04:22:28
These languages provide modules which are inherently concurrent and can handle asynchronous messages pretty neat (through ports). Keeping aside the fact that they cannot spawn module instances at runtime, do they qualify as actor based programming languages? Thanks EDIT: What I'm really looking for is how well the language semantics can be used to "model" actors, rather than how a simulator would handle the code (of course, they are all event-driven underneath; and further down, we end up with transistors :-) ). So if I create a bunch of Ip4Routers like this, module Ip4Router ( inout interface

Difference between @(posedge Clk); a<= 1'b1; and @(posedge Clk) a<= 1'b1;

由 我只是一个虾纸丫 提交于 2019-12-08 16:41:55
问题 Is there any difference between @(posedge Clk); a<= 1'b1; and @(posedge Clk) a<= 1'b1; Note the semicolon after Clk. I came across similar lines of code when I was browsing through a testbench. I did some simple experiments and I could not find any differences during simulation. Will the sequence of execution for the code following these lines change in any way due to the presence/absence of the semicolon? 回答1: You're correct -there's no behavioural difference. The semicolon version is: Wait.

Reading and Writing to a file simultaneously

由 邮差的信 提交于 2019-12-08 10:59:59
问题 I have a module in written in System Verilog that dumps the contents of the SRAM into a file. I would like to read from this file and use the data in a separate program written in python, but in real time. I don't have much control over the writing from the verilog code. Is it possible to somehow manage the two read and writes? Currently when it reads from the file, there is a (seemingly) random number inserted at the start of every line and that throws off the parsing. I assume these
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