what is the difference between automatic and static task,why we cant pass by reference to a static task

问题

What is the difference between the static and automatic tasks.

program class_ref;
  int index,value;

 class holding_values;
   int ass_array[*];
   task assign_value (int value,int index);
       ass_array[index] = value;
   endtask 

   function void disp(int index);
       $display("%t  %M:ASSOSIATIVA VALUE%d ",$time,ass_array[index]);
   endfunction

endclass

initial begin
    holding_values  obc;
    index =5;
    value =88;
    obc = new();
    map(obc,value);
    obc.disp(index);
end


task map(ref holding_values obc,ref int value );
    value +=5;
    obc.assign_value(value,index);
    obc =null;
endtask

endprogram

if this code is executed it will give the error

reference argument is illegal inside static task-function declaration

if task "map" is made to automatic the program runs.

Why do we need to make task automatic? What is the difference between static and automatic tasks?

回答1:

For a static task, multiple invocations of the same task will reference the same local variables. For an automatic task, the local variables will be unique to each invocation of the task.

This means that for the following task:

task some_task();
  int foo = 5;
  // ...
endtask

if we define it static, then all invocations will see the same value for foo (i.e. foo will be shared between them). This means that changing the value in one thread will make all others also see the change.

If we were to define some_task() automatic, then each invocation would have its own local copy of foo, totally independent of the others. Changing foo in one thread won't have any effect in others.

回答2:

I think it is also worth noting that in system-verilog every task/function defined in a module/program or standalone is by default static, but if defined in a class is by default automatic (as in any other programming language). I would suppose that the reason for this is that verilog is not a "normal language" but a HDL language, always block in a module are by definition static.

function add();
   int i;
   i++;
   $display("i=%0d", i);

endfunction


module try;


   initial begin
      add();
      add();
      $finish;
   end
endmodule

output:

i=1
i=2
$finish called from file "try.sv", line 15

回答3:

No one addressed the "why we can't pass by reference to a static task" portion of the question. The LRM doesn't provide a 'why' as far as I can tell, but I can hazard a guess and ask a further question.

Guess: Garbage collection is at issue. By passing references to static functions, you have in effect, kept them alive forever. The LRM states that even if an array is deleted outside the task, if an element of the array was passed by reference to the task, then that element must be kept alive. It still won't be visible to the rest of the simulation after the array is deleted. This would be an interesting way to quickly run into out-of-memory errors.

Question: Is it possible that arguments to static tasks have static lifetimes? If so, could a referenced handle to an object be overwritten with the pointer to another object if the task was called again with a different argument value?

来源：https://stackoverflow.com/questions/28021666/what-is-the-difference-between-automatic-and-static-task-why-we-cant-pass-by-ref

标签

system-verilog