system-verilog

How to create random dynamic 2D arrays in SystemVerilog?

由 微笑、不失礼 提交于 2019-12-08 10:32:33
问题 I know how to create a random dynamic array in SystemVerilog: class packet; rand int unsigned len; rand byte data[]; constraint size_con { len < 2000; data.size = len; } endclass: packet but I can't figure out how to use random 2d dynamic array? class video_frame; rand int unsigned width; rand int unsigned height; rand int unsigned data[][]; constraint size_con { width >= 8; width <= 4096; height >= 8; height >= 2048; // How to constraint data.size to be [height, width] } endclass: video

Array of systemverilog interfaces with different inputs

由 梦想的初衷 提交于 2019-12-08 09:45:41
问题 I would like to instantiate an array of systemverilog interfaces where each array element uses a different input. If all the elements use the same input, then the instantiation is simple: x_if x_IF[`NUM_INTERFACES](clk); Here, if `NUM_INTERFACES is 2 , then the clk input goes to both x_IF[0] and x_IF[1] . But if I also have reg clk[`NUM_INTERFACES]; how do I instantiate x_IF so that clk[0] is input to x_IF[0] and clk[1] is input to x_IF[1] ? This is a simple example; I am looking forward to

Can Verilog/Systemverilog/VHDL be considered actor oriented programming languages?

由 回眸只為那壹抹淺笑 提交于 2019-12-08 05:13:28
问题 These languages provide modules which are inherently concurrent and can handle asynchronous messages pretty neat (through ports). Keeping aside the fact that they cannot spawn module instances at runtime, do they qualify as actor based programming languages? Thanks EDIT: What I'm really looking for is how well the language semantics can be used to "model" actors, rather than how a simulator would handle the code (of course, they are all event-driven underneath; and further down, we end up

Dynamic array of interfaces in SV

由 混江龙づ霸主 提交于 2019-12-08 04:23:47
问题 In SV LRM 2012 they are saying that interface_instantiation ::= interface_identifier [ parameter_value_assignment ] hierarchical_instance { , hierarchical_instance } ; When searching meaning of hierarchical_instance you can find hierarchical_instance ::= name_of_instance ( [ list_of_port_connections ] ) name_of_instance ::= instance_identifier { unpacked_dimension } Finally, it can found that unpacked_dimension ::= [ constant_range ] | [ constant_expression ] I would like to read it so that

What is need of Assign/Deassign in Verilog?

由 a 夏天 提交于 2019-12-08 03:59:38
问题 I am here giving here 2 Verilog modules, which during simulation behaves same. But I don't understand that why to use assign / deassign in these modules, i.e. what is the difference between these 2 codes? // Code 1 - Without assign-deassign module dff (q,qbar,clk,reset,d) input clk, reset, d; output reg q, qbar; always @ (posedge reset, negedge clk) begin if(reset) begin q=1; qbar=0; end else begin q=d; qbar=~d; end end endmodule // Code 2 - With assign-deassign module dff (q,qbar,clk,reset,d

How is backdoor access for registers, physically implemented in a VLSI design?

由 故事扮演 提交于 2019-12-08 02:20:17
问题 Synthesizable register(s) can conventionally be verified using access technique that use address & data buses ( these buses are very much part of the actual hardware present on the silicon chip ). But this conventional access technique consumes finite time. Register Abstraction Layer (RAL) with UVM is a very efficient way of verifying RTL registers in your design. One of the key features of this methodology is 'backdoor access' , by virtue of which one can access ( i.e. read from or write

How to write a makefile where the compiled object files are in a different directory with a different name?

由 孤街浪徒 提交于 2019-12-07 23:21:18
问题 So I'm trying to write a Makefile to use with QuestaSim and systemverilog files. If you don't know what that is (and most people won't) then don't worry, it's not that relevant to my problem. I have a project director containing: src/ work/ Makefile the src/ directory contains several directories which each contain source files. the work/ directory doesn't initially exist, and is created by the makefile. when I call my "compiler" which is called vlog, on a .sv file a directory gets created in

Defining parameters from command line in (system)verilog simulation

由 隐身守侯 提交于 2019-12-07 20:59:00
问题 I have a module ''constrained'' with several delays as parameters. I want to simulate all the possible configuration of the delays in the module. As I have a lot of configuration to test, I do not want to instantiate all the configuration possible in the same testbench. The idea I had was to launch one simulation for each configuration. I thought about generating a simulation script that will launch the simulation for each delay configuration. The problem is that I cannot manage to override

inputs without type in system verilog

由 ≯℡__Kan透↙ 提交于 2019-12-07 20:08:30
问题 I've encountered in an example for a system verilog code decleration of inputs and outputs for a module without stating their type, e.g logic , wire ... module mat_to_stream ( input [2:0] [2:0] [2:0] a,b, input newdata, input rst, clk, output [2:0] [7:0] A_out, B_out); ...rest of code... What is the diffrence between stating logic and not stating any type? 回答1: There is no difference between stating logic and not stating any type. input newdata, is equivalent to input logic newdata, The

What is need of Assign/Deassign in Verilog?

由 安稳与你 提交于 2019-12-07 15:35:36
I am here giving here 2 Verilog modules, which during simulation behaves same. But I don't understand that why to use assign / deassign in these modules, i.e. what is the difference between these 2 codes? // Code 1 - Without assign-deassign module dff (q,qbar,clk,reset,d) input clk, reset, d; output reg q, qbar; always @ (posedge reset, negedge clk) begin if(reset) begin q=1; qbar=0; end else begin q=d; qbar=~d; end end endmodule // Code 2 - With assign-deassign module dff (q,qbar,clk,reset,d) input clk, reset, d; output reg q, qbar; always @ (negedge clk) begin q=d; qbar=~d; end always @
订阅 system-verilog