system-verilog | 易学教程

How to parameterize a case statement with don't cares?

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问题 I have a wire called input and I want to detect the number of leading I am trying to create a module which uses the case statement below to change the output data depending on the number of leading zeros. However the size of the input is parameterizable. If X was a fixed value of 4, I would just create a case statement, case (input) 4'b0001 : o_data = {i_data[0]}; 4'b001x : o_data = {i_data[1],1'b0}; 4'b01xx : o_data = {i_data[2],2'b0}; 4'b1xxx : o_data = {i_data[3],3'b0}; default : o_data =

verilog $readmemh takes too much time for 50x50 pixel rgb image

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问题 I am trying to compile a verilog code for FPGA programming where I will implement a VGA application. I use QuartusII and Altera. I am trying to use readmemh properly for acquiring a picture pixel by pixel. For now, I have converted a picture into rgb texts using matlab. Each has the following format and nothing else (example): 03 A0 15 B7 ... At the moment I am not getting any syntax errors however I had to define three registers each having 50x50 = 2500 bits and it is compiling quite slower,

Using burst_read/write with register model

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问题 I've a register space of 16 registers. These are accessible through serial bus (single as well as burst). I've UVM reg model defined for these registers. However none of the reg model method supports burst transaction on bus. As a workaround I can declare memory model for same space and whenever I need burst access I use memory model but it seems redundant to declare 2 separate classes for same thing and this approach won't mirror register values correctly. create a function which loops for

TAP (Test Anything Protocol) module for Verilog or SystemVerilog

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问题 Is there a TAP (Test Anything Protocol) implementation for Verilog? It would be nice because then I could use prove to check my results automatically. Update: 10/9/09: It was asked why not use assertions. Partly TAP gives me some good reporting such as number of files and number of tests. It also can be used with smolder for reporting of progress over time. 10/12/09: I'm looking for a minimal implentation with number of tests at the beginning and end and the ok, diag and fail functions. is()

What is the difference between single (&) and double (&&) ampersand binary operators?

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问题 In IEEE 1800-2005 or later, what is the difference between & and && binary operators? Are they equivalent? I noticed that these coverpoint definitions behave identically where a and b are of type bit : cp: coverpoint a & b; cp: coverpoint a && b; 回答1: && is a boolean operator which we call "logical AND". This doesn't mean that it must operate on boolean operands, but that its return type is boolean. In SV, boolean means: 1'b1 \\ true 1'b0 \\ false 1'bx \\ undef When logical AND operates on

inputs without type in system verilog

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I've encountered in an example for a system verilog code decleration of inputs and outputs for a module without stating their type, e.g logic , wire ... module mat_to_stream ( input [2:0] [2:0] [2:0] a,b, input newdata, input rst, clk, output [2:0] [7:0] A_out, B_out); ...rest of code... What is the diffrence between stating logic and not stating any type? There is no difference between stating logic and not stating any type. input newdata, is equivalent to input logic newdata, The SystemVerilog IEEE Std (1800-2009) describes this in section: "23.2.2.3 Rules for determining port kind, data

Defining parameters from command line in (system)verilog simulation

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I have a module ''constrained'' with several delays as parameters. I want to simulate all the possible configuration of the delays in the module. As I have a lot of configuration to test, I do not want to instantiate all the configuration possible in the same testbench. The idea I had was to launch one simulation for each configuration. I thought about generating a simulation script that will launch the simulation for each delay configuration. The problem is that I cannot manage to override the parameters of the module with the values retrieved from the command-line. I used $value$plusargs(

UVM: illegal combination of driver and procedural assignment warning

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问题 I have a UVM testbench for a small block in my chip. In this there is an agent with a driver that drives data on a virtual interface which looks something like this: interface my_if (input bit clk); logic [3:0] opcode; // Clocking block for the driver clocking drvClk @(posedge clk); output opcode; endclocking // Clocking block for the monitor clocking monClk @(posedge clk); input opcode; endclocking endinterface I use this interface in my driver like this: class my_driver extends uvm_driver #

How to emulate $display using Verilog Macros?

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问题 I want to create a macro with multiple parameters just like $display. My code looks like this but it doesn't work. `define format_macro(A) \ $write("%s", $sformatf(A)); \ This is how I called format_macro. `format_macro("variable = %d", variable) How can I do this? 回答1: I want to create a macro with multiple parameters just like $display. You can't. Verilog and SystemVerilog do not support variadic macros. Here is a workaround if your goal is to use this for formatting strings or output, and

Integrating fftw C function calls inside system verilog code

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I have installed fftw C library succefully on my linux system. Here is more info about fftw c => http://www.fftw.org/ I have a sample C code which can call fftw C functions successfully. Below is a C ccode and command to run the C code: Code: #include <stdio.h> #include <stdlib.h> #include <stdint.h> #include <math.h> #include <fftw3.h> int main(void) { double FFT_in[] = {0.1, 0.6, 0.1, 0.4, 0.5, 0, 0.8, 0.7, 0.8, 0.6, 0.1,0}; double *IFFT_out; int i,size = 12; fftw_complex *middle; fftw_plan fft; fftw_plan ifft; middle = (fftw_complex*) fftw_malloc(sizeof(fftw_complex)*size); IFFT_out =