system-verilog

I have a wire called input and I want to detect the number of leading I am trying to create a module which uses the case statement below to change the output data depending on the number of leading zeros. However the size of the input is parameterizable. If X was a fixed value of 4, I would just create a case statement, case (input) 4'b0001 : o_data = {i_data[0]}; 4'b001x : o_data = {i_data[1],1'b0}; 4'b01xx : o_data = {i_data[2],2'b0}; 4'b1xxx : o_data = {i_data[3],3'b0}; default : o_data = 4'b0000; endcase But with variable X, how do I define all cases? This question is similar to this one:

I'm trying to instantiate some modules in Verilog using a generate block since I'm going to be instantiating a variable amount of them. genvar i; generate for (i=1; i<=10; i=i+1) begin status whatever_status ( .clk(clk), .reset_n(reset_n), .a(a[i]), .b(b[i]), .out(out[i]) ); end endgenerate a & b are declared as input arrays to the parent module and out is declared as a array of wires. What am I doing wrong here? Is this not allowed in Verilog? Quartus is telling me: Error (10644): Verilog HDL error at driver.v(63): this block requires a name Line 63 is the for loop above. Any help is

I am using RedHat EL 4. I am using Bash 3.00.15. I am writing SystemVerilog and I want to emulate stdin and stdout. I can only use files as the normal stdin and stdout is not supported in the environment. I would like to use named pipes to emulate stdin and stdout. I understand how to create a to_sv and from_sv file using mkpipe, and how to open them and use them in SystemVerilog. By using "cat > to_sv" I can output strings to the SystemVerilog simulation. But that also outputs what I'm typing in the shell. I would like, if possible, a single shell where it acts almost like a UART terminal.

Is there a TAP ( Test Anything Protocol ) implementation for Verilog? It would be nice because then I could use prove to check my results automatically. Update: 10/9/09: It was asked why not use assertions. Partly TAP gives me some good reporting such as number of files and number of tests. It also can be used with smolder for reporting of progress over time. 10/12/09: I'm looking for a minimal implentation with number of tests at the beginning and end and the ok, diag and fail functions. is() would really nice, but not necessary. DaveParillo I don't think there is a native TAP implementation

I have a UVM testbench for a small block in my chip. In this there is an agent with a driver that drives data on a virtual interface which looks something like this: interface my_if (input bit clk); logic [3:0] opcode; // Clocking block for the driver clocking drvClk @(posedge clk); output opcode; endclocking // Clocking block for the monitor clocking monClk @(posedge clk); input opcode; endclocking endinterface I use this interface in my driver like this: class my_driver extends uvm_driver #(my_tr); my_if vif; ... virtual task run_phase(uvm_phase phase); super.run_phase(phase); forever begin

In SystemVerilog hierarchical modules can be connected by simple data types, complex data types (structs, unions, etc), or interfaces. The feature that I am interested in is aggregating all signals between two modules in one place which simplifies maintenance of the code. For example in the following one change s_point's definition without changing the declarations of m1, m2, and top: typedef struct { logic [7:0] x; logic [7:0] y; } s_point; // named structure module m1 (output s_point outPoint); // endmodule module m2 (input s_point inPoint); // endmodule module top (); s_point point; m1 m1