system-verilog

How do I read an environment variable in Verilog ? (Running on a VCS simulator) I am trying to accomplish File=$fopen("$PATH/FileName","r"); $PATH is an environment variable. You can simply use SystemVerilog DPI for getting environment. And because getenv is a standard C library for every POSIX platform, so you do not need to implement your own getenv() equivalent function for the function definition again. Example code in SV. import "DPI-C" function string getenv(input string env_name); module top; initial begin $write("env = %s\n", {getenv("HOME"), "/FileName"}); end endmodule Running

Following up on this question about the difference between packed and unpacked vectors in SV, why would I ever want to use unpacked vectors? Packed vectors have these advantages that unpacked vectors don't have: You can perform bit-wise operations on them You can perform arithmetic operations on them You can take slices of them You can copy them as a whole vector You can do anything you can with un packed vectors (to the best of my knowledge) What advantage do unpacked vectors have over packed vectors? Biswajit Khandai There is another reason why I like to use unpacked. With unpacked, there is

I am trying to make a module (a DSP in my case) with a standardized memory interface in SystemVerilog, and would like the variables in the module to size automatically based on the bus widths in the attached interface. My rationale: this makes the code more portable by allowing it to auto-size to any connected interface, instead of requiring an HDL coder to pass in parameters that tell the module the widths of all the interface busses that will connect to it (not that this would be terrible, it just seems cleaner without the parameters). I can't seem to get this to work, however. Here's an

I am clock gating some latch and logic in my design. I don't have much experience in synthesis and place & route. What is the proper way to implement clock gating in RTL? Example1: always_comb begin gated_clk = clk & latch_update_en; end always_latch begin if(gated_clk) begin latch_data <= new_data; end end Example2: I stumbled into a RTL examples while doing some research about good practices in RTL clock gating. That example implemented the above code like this: clock_gator cg_cell (.clk(clk), .en(latch_update_en), .scan_en(scan_en_in), .gated_clk(gated_clk)); always_latch begin if(gated_clk

I want to create a clock in my top level testbench whose period can be controlled from the test. What I did was set the period into the uvm_config_db and get it back in the testbench. I had to put in a #1 to make sure that the build phase was finished, otherwise the get returned the wrong value: module testbench_top; int clk_period; bit clk = 0; initial begin #1; void'(uvm_config_db #(int) ::get(null, "uvm_test_top.env", "clk_period", clk_period)); // Create clk forever begin #(clk_period/2) clk = !clk; end end I am annoyed by the #1. Is there a better way to check that the config has been set

I have a preprocessor macro that represents a hierarchical path into my design. Example: `define HPATH top.chip.block I need to construct a string which holds the value of `HPATH , so in my example the string should equal top.chip.block . Is there a way to construct such a string? None of the following attempts worked: string hpath; hpath = "`HPATH"; // Results in hpath = "`HPATH" hpath = \"``HPATH\"; // Doesn't compile hpath = `HPATH; // Doesn't compile I want hpath to be equivalent to doing this assignment hpath = "top.chip.block" , but by using `HPATH instead of specifying the path again. I