Best way to access the uvm_config_db from the testbench?

问题

I want to create a clock in my top level testbench whose period can be controlled from the test. What I did was set the period into the uvm_config_db and get it back in the testbench. I had to put in a #1 to make sure that the build phase was finished, otherwise the get returned the wrong value:

module testbench_top;
  int clk_period;

  bit clk = 0;

  initial begin
    #1;    
    void'(uvm_config_db #(int) ::get(null, "uvm_test_top.env", "clk_period", clk_period));
    // Create clk
    forever begin
      #(clk_period/2) clk = !clk;
    end
  end

I am annoyed by the #1. Is there a better way to check that the config has been set? Can I somehow block until start_of_simulation_phase?

回答1:

I found it buried in the class reference: You can access the global singleton versions of each phase with <phase name>_ph. Then I can use the wait_for_state function to block until the start of the start of simulation phase. Simulated and it seems to work:

module testbench_top;
  int clk_period;

  bit clk = 0;

  initial begin
    start_of_simulation_ph.wait_for_state(UVM_PHASE_STARTED);    
    if(!uvm_config_db #(int) ::get(null, "uvm_test_top.env", "clk_period", clk_period))
      `uvm_fatal("CONFIG", "clk_period not set");
    // Create clk
    forever begin
      #(clk_period/2) clk = !clk;
    end
  end

回答2:

Another alternative that can help is wait_modified function of uvm_config_db... Here is the excerpt from uvm reference manual

wait_modified:

static task wait_modified(uvm_component cntxt,
                          string  inst_name,
                          string  field_name)

Wait for a configuration setting to be set for field_namein cntxtand inst_name. The task blocks until a new configuration setting is applied that effects the specified field.

来源：https://stackoverflow.com/questions/19840611/best-way-to-access-the-uvm-config-db-from-the-testbench

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verilog

system-verilog

uvm