uvm

Changing clocking block clock polarity on the fly

扶醉桌前 提交于 2021-02-10 14:39:05
问题 I am creating UVM VIP which is able to switch its clock polarity. Clocking block is used in the interface. For example, a monitor should sample the data using posedge or negedge of incoming clock depending on UVM configuration - and this polarity change can happen on the fly. This can be implemented as follows: // In the interface, two clocking blocks are defined // one for posedge (passive_cb), one for negedge (passive_cbn). task wait_clock_event(); if (cfg.pol == 0) @vif.passive_cb; else

UVM中的regmodel建模(二)

帅比萌擦擦* 提交于 2020-03-12 04:40:17
UVM的寄存器模型,对一个寄存器bit中有两种数值,mirror值,尽可能的反映DUT中寄存器的值。expected值,尽可能的反映用户期望的值。 几种常用的操作: read/write:可以前门访问也可以后门访问,如果在env的顶层定义过uvm_auto_predict(1),则UVM会在这两个操作后自动调用do_predict函数 来更新寄存器模型中的mirror值。 peek/poke:只用于后门访问,而且完全不管硬件的行为,如向只读寄存器写数据,仍可以写入。应用很少。会自己更新mirror值和expected值。 get/set:得到或设置寄存器模型的期望值。 update操作:可以使用前门访问,也可以使用后门访问,检查期望值与镜像值是否一致,如不一致,则向DUT写入期望值。 通过枚举结构uvm_path_e来定义。 mirror操作:用于读取DUT中寄存器的值并将它们更新到寄存器模型中。可以前门访问也可以后门访问。两种的应用场景:1)check选项关闭, 仿真中不断调用。2)check选项打开,用在结束时,检查DUT与寄存器模型的值是否相同。 predict操作:人为的根据DUT来更新寄存器模型中的镜像值。但同时又不对DUT进行任何操作。此时的uvm_path_e是UVM_PREDICT_DIRECT。 可以通过加monitor在寄存器总线上。检测到uvm_reg

UVM Tutorial for Candy Lovers – 23. Jelly Bean Taster in UVM 1.2

余生长醉 提交于 2020-02-23 13:15:51
My first series of UVM tutorials (#1 to #6) was posted more than three years ago. Since then, UVM (and my knowledge about it) has evolved and I always wanted to update my articles and code. But it was not easy because my article and code were tightly coupled and some comments from the readers even referred to the specific lines of code. UVM 1.2 About two months ago, Accellera released new UVM 1.2 and it motivated me to update my jelly bean taster. I thought it’s time to overhaul. Interestingly though, my code required almost no modifications. The only change I made was taking advantage of new

UVM Systemverilog 国外学习网站

雨燕双飞 提交于 2020-02-22 05:50:17
http://www.testbench.in/ https://verificationacademy.com/ mentor的学习论坛,里面有UVM cookbook 同时还包含练习代码以及testbench的模板代码 (https://verificationacademy.com/cookbook/code-examples) https://www.chipverify.com/ chip verify 相比其他网站,这个网站上的内容更基础实用。 https://quqi.gblhgk.com/s/362912/vrPCecJbyafAd92H The UVM Primer 基础实用,必看。 https://www.edaplayground.com/ 在线EDA仿真网站 https://vlsi.pro/ 一个博客 sv一些内容 https://www.doulos.com/ 一个培训网站,UVM code 规范 (Easier UVM Coding Guidelines)以及testbench脚本生成工具(Easier UVM Code Generator) http://cluelogic.com/ Providing the clues to solve your verification problems http://www

UVM的三种端口类型

懵懂的女人 提交于 2020-02-04 12:47:16
uvm中有三种端口类型:按优先级分别为prot(发起者)、export(接收者)、imp(缓存),其中对应get、put、transport、peek等几种操作。 加上nonblocking和blocking表示只能用于阻塞(等待)或非阻塞(不等待)处理方式,不加表示均可用。 imp加上et、put、transport、peek、nonblocking和blocking等操作方式,不是发起相应类型的操作,而是表示可以和相应类型的port或export端口进行通信。 两个组件进行数据通信前必须先建立连接关系,UVM中使用connect函数来建立连接关系。A是发起者,B是接收者,连接代码为:A.port.connect(B.export),不能写成B.export.connect(A.port)。 定义: uvm_blocking_get_port # (T):T表示端口传输的数据类型; uvm_nonblocking_peek_imp # (T, IMP):IMP表示实现这个端口操作的component。 来源: CSDN 作者: hk604296024 链接: https://blog.csdn.net/hk604296024/article/details/104166585

UVM phase机制(三)objection机制

隐身守侯 提交于 2020-01-15 08:23:01
在上一篇博客UVM phase机制(二)中,我们有介绍到run_phase以及12个run_time_phase是如何运转起来的,但是留了一个小问题就是objection,想要run必须raise_objection,要想结束run必须drop_objection。下面我们详细分析一下为什么会这样 在运行到run_node的时候,是这样一个执行结构, fork fork env.run_phase(uvm_phase phase); join_none fork uvm_test_top.run_phase(uvm_phase phase); join_none fork top.run_phase(uvm_phase phase); join_none join_none 但是,最终完整的执行结构是 fork fork env.run_phase(uvm_phase phase); join_none fork uvm_test_top.run_phase(uvm_phase phase); join_none fork top.run_phase(uvm_phase phase); join_none join_none #0; fork begin fork process(0);//junp process(1);//objection process(2);/

UVM Tutorial for Candy Lovers – 13. Configuration Database

北城以北 提交于 2020-01-09 04:20:05
This post will explain how configuration database ( uvm_config_db ) works. In Configurations , we used the uvm_config_db to store a jelly_bean_if , a jelly_bean_env_config , and two jelly_bean_agent_config s. This post will analyze how a configuration data is stored and retrieved. The class diagram related to the configuration database is shown below. Note that we only showed the classes related to the jelly_bean_if and jelly_bean_agent_config to avoid clutter. UVM standard library classes are shown in pink, while the UVM classes specialized with the jelly_bean_transaction type are shown in

Failing to write in systemverilog mailbox

别等时光非礼了梦想. 提交于 2019-12-25 12:31:52
问题 I'm using mailbox in a UVM SV test bench and facing some issue while trying to write in mailbox. My code looks like bellow: class my_seqyuence extends uvm_sequence; mailbox data; some_user_defined_type mydata; function new(string name = "my_sequence"); super.new(name); data=new(); endfunction task body(); forever begin // blocking-get. program is blocked here... not why get is not returning...! data.get(mydata); decode_mydata_and_do_something_here; end endtask function void writetrans(some

running UVM phases on multiple cores

我的梦境 提交于 2019-12-25 02:08:50
问题 How can we devote the individual phases in UVM like run, elaboration, build etc to run on multiple cores of the system. How can this be done through coding. 回答1: As far as I know, multicore support is something you can't influence through coding. It's something your simulator either has or hasn't. Even if you could, you have the problem that your build, connect, run, etc. phase must execute in sequence. 来源: https://stackoverflow.com/questions/22296583/running-uvm-phases-on-multiple-cores

Where to use uvm_blocking_put_port and uvm_analysis_port?

泄露秘密 提交于 2019-12-23 03:27:09
问题 What is the difference between port and analysis port ? Where to use uvm_blocking_put_port and where to use uvm_analysis_port ? What is advantage of uvm_analysis_port over uvm_blocking_put_port ? 回答1: Port connection is used to connect two independent blocks(components). Both uvm_blocking_put_port and uvm_analysis_port used to transfer data from producer to consumer. (1) uvm_blocking_put_port: Used for data transfer from a single producer to a single consumer. (2) uvm_analysis_port: Used for