uvm | 易学教程

setting the Verbosity only for few /sequences/objects/interfaces in uvm?

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问题 How do I control the verbosity of certain components so that I can set a verbosity to only few of the components? Lets say, for example in the verification of a particular feature, the test, few set of components/sequences/objects/interfaces etc are involved. I would like to set the verbosity of only these to be UVM_HIGH . I do not want to set the global severity to be set UVM_HIGH since lot of unrelated debug messages could come in which might increase the log size. What would be a cleaner

Regex in SV or UVM

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问题 What functions do I need to call to use Regular Expressions in Systemverilog/UVM? Note: I'm not asking how to use regular expressions, just method names. 回答1: First, if you want to use regular expression, you'll need to make sure you're using a UVM library compiled together with its DPI code (i.e. the UVM_NO_DPI define isn't set). The methods you want to use are located in dpi/uvm_regex.svh . The main function is uvm_re_match(...) , which takes as an argument a regular expression and the

寄存器（RAL）模型中的set update实现写操作

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在进行寄存器写操作时，还有一种方法是使用set,update的方式下面来介绍一下首先是set方法 function void uvm_reg::set(uvm_reg_data_t value, string fname = "", int lineno = 0); // Split the value into the individual fields m_fname = fname; m_lineno = lineno; foreach (m_fields[i]) m_fields[i].set((value >> m_fields[i].get_lsb_pos()) & ((1 << m_fields[i].get_n_bits()) - 1)); endfunction: set 其实最终调用的field的set方法，根据之前设置的field的access来设置field的m_desired value，最终的效果就是设置reg的desired value task uvm_reg::update(output uvm_status_e status, input uvm_door_e path = UVM_DEFAULT_DOOR, input uvm_reg_map map = null, input uvm_sequence_base parent = null

How to perform uvm_do_on without randomization?

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问题 I have a virtual sequencer from which I execute three transactions in parallel, each one on its corresponding sequencer. So I have something like this: class top_vseqr extends uvm_seqr extends uvm_sequencer; type_a_seqr seqr_a; type_b_seqr seqr_b; type_c_seqr seqr_c; ... endclass: top_vseqr class simple_vseq extends uvm_sequence; `uvm_declare_p_sequencer(top_vseqr) type_a_seq seq_a; type_b_seq seq_b; type_c_seq seq_c; ... virtual task body(); fork `uvm_do_on(seq_a, p_sequencer.seqr_a) `uvm_do

uvm set_inst_override for a sequence

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问题 I'm trying to override a sequence by instance. An example code will describe it best: class my_vir_seq extends base_vir_seq; my_seq_c seq1, seq2; `uvm_object_utils_begin(my_vir_seq) `uvm_field_object(seq1, UVM_ALL_ON) `uvm_field_object(seq2, UVM_ALL_ON) `uvm_object_utils_end `uvm_declare_p_sequencer(v_seqr) function new(string name = "my_vir_seq"); super.new(name); endfunction // new virtual task body(); `uvm_do_on(seq1, p_sequencer.my_seqr) `uvm_do_on(seq2, p_sequencer.my_seqr) endtask //

I am getting an error while trying to pass the data from scoreboard to sequence, how to get rid of it?

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问题 I am new to UVM and I am trying to verify a memory design where I am trying to run a write sequence multiple times followed by read sequence same number of times so that I could read the same addresses I am writing to, and compare. For this I tried to create a new class extended from uvm_object with a queue to store the addresses I am writing to, so that I could use them in read seq and I am instantiating this class in the scoreboard and then sending the handle of class to the read sequence

UVM testbench - What is the “UVM” way to connect two different drivers to same interface?

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问题 In my Testbench, I have an interface that I need to drive. The interface can be driven in 2 different modes, with each mode having its own driver protocol and transaction type. So far, I have designed both uvm_agents separately. Now, I need a way to swap one or the other in, depending on the testcase I am running. I also want to do this in the way that best fits with UVM philosophy. My best method that I could come up with is: in my uvm_env, getting a uvm_db_config parameter from the test

Get system time in VCS

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问题 Is there way to get system time in VCS/UVM ? I am looking for something similar to Perl's localtime(time) . Is there way to print system time for every uvm_info printed ? 回答1: One way is to use $system() to run any system command, including system' date command. initial begin $system("date"); end From IEEE 1800 LRM: $system makes a call to the C function system(). The C function executes the argument passed to it as if the argument was executed from the terminal. $system can be called as

How is backdoor access for registers, physically implemented in a VLSI design?

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问题 Synthesizable register(s) can conventionally be verified using access technique that use address & data buses ( these buses are very much part of the actual hardware present on the silicon chip ). But this conventional access technique consumes finite time. Register Abstraction Layer (RAL) with UVM is a very efficient way of verifying RTL registers in your design. One of the key features of this methodology is 'backdoor access' , by virtue of which one can access ( i.e. read from or write

uvm macro (常用的）[uvm_info]

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`uvm_info(1,2,3) 1:ID 2:MSG 3:VERBOSITY 如果VERBOSITY级别低于reporter组件定义的级别，就会调用uvm_report_info 举例： --> `uvm_info("DRV_RUN",{req.sprint()},UVM_HIGH) --> `uvm_info("MY_INFO",$sformatf("pval:%0d",val),UVM_LOW) 也可以自行定制： `uvm_info_begin("MYID","this is a message for test...",UVM_LOW) `uvm_message_add_tag("author”,ZHUHAI） `uvm_message_add_object(my_obj) `uvm_info_end 来源： CSDN 作者：竹海EE----WMY 链接： https://blog.csdn.net/weixin_41241296/article/details/79383663