system-verilog

I'm currently using modelsim SE 5.8e. It doesn't support SystemVerilog. I need to use SystemVerilog for design and validation of my project. Any idea which version of Modelsim supports both design and validation subset of sytemverilog well? I used VCS before and trying to find it if I can use Modelsim instead of VCS for simulation. Thanks in advance! According to this table , ModelSim supports SystemVerilog design features, but not verification features. This means that it probably does not support classes, randomization, or the coverage features of SV. The latest simulator platform from

I have write the code Alu.v module ALU( src1_i, src2_i, src3_i, src4_i, ctrl_i, result_o, zero_o ); //I/O ports input [32-1:0] src1_i; input [32-1:0] src2_i; input [4-1:0] src3_i;//shmat is 5 bits instruction[10:6] input [15-1:0] src4_i;//ori have to deal with 'zero-extended' number input [4-1:0] ctrl_i; output [32-1:0] result_o; output zero_o; //Internal signals reg [32-1:0] result_o; wire zero_o; //Parameter assign zero_o = (result_o == 0); //Main function always @(*) begin case(ctrl_i) 0 :result_o <= src1_i & src2_i;//and 1 :result_o <= src1_i | src2_i;//or 2 :result_o <= src1_i + src2_i;/

I think the question sums it up pretty well as to what I want: passing the value of a variable to a macro in SystemVerilog. For example, what I want: Say, there are 4 signals by the name of abc_X_def and I want to initialize all of them to 0. So, without macros: abc_0_def = 4'b0000; abc_1_def = 4'b0000; abc_2_def = 4'b0000; abc_3_def = 4'b0000; Now, the code that I have written is having a problem: `define set_value(bit) abc_``bit``_def = 4'b0000 for (int i = 0; i < 4; i++) begin `set_value(i); end The error is that it's trying to find the signal abc_i_def which is obviously wrong. Just

For example: IOs A and B are connected have a 10ns io-to-io delay between them. The IOs run at 500MHz (2ns period). By default Verilog uses inertial delay which acts as a filter. Therefore defining the interconnect wire as wire #(10ns) io; will not work since it will filter out the data. wire #(10ns) io; assign io = io_a_en ? a_data_500MHz : 'z; assign io = io_b_en ? b_data_500MHz : 'z; Transport delay is unidirectional. Creating one for each direction on an IO will cause multiple drivers and a feedback loop. always @(a) b_reg <= #(10ns) a; always @(b) a_reg <= #(10ns) b; assign a = b_reg; //

I'm trying to make BCD Counter using Verilog that will be connected to 7-segment decoder. After I synthesize it, the error occured like this: Multi-source in Unit <BCDcountmod> on signal <BCD0<3>>; this signal is connected to multiple drivers.> **And more..... ***Any solution?* ( Here's my code below ) module BCDcountmod( input Clock, Clear, up, down, output [3:0] BCD1_1, BCD0_0 ); reg [3:0] BCD1, BCD0; //reg [3:0] BCD1_1, BCD0_0; always @(posedge Clock) begin if (Clear) begin BCD1 <= 0; BCD0 <= 0; end end always @(posedge up) begin if (BCD0 == 4'b1001) begin BCD0 <= 0; if (BCD1 == 4'b1001)

I am trying to create a for loop that assigns different values to a logic array given the iteration of the loop. So, for instance, let's say I am trying to instantiate two different bricks, both with a width of 10 and height of 5. Let's also say that each of these values are 10 bits. For two bricks, I have the code: logic[19:0] Brick_Width; logic[19:0] Brick_Height; Where the first brick's width and height will be assigned into the most significant 10 bits and the second's in the least significant 10 bits. This is the code that I currently have for this: int i = 19; initial begin for(i=19; i>

What functions do I need to call to use Regular Expressions in Systemverilog/UVM? Note: I'm not asking how to use regular expressions, just method names. First, if you want to use regular expression, you'll need to make sure you're using a UVM library compiled together with its DPI code (i.e. the UVM_NO_DPI define isn't set). The methods you want to use are located in dpi/uvm_regex.svh . The main function is uvm_re_match(...) , which takes as an argument a regular expression and the string to match against. This is basically a wrapper around the regexec(...) C function found in the regex.h