Modelsim support for SV

Question

I'm currently using modelsim SE 5.8e. It doesn't support SystemVerilog. I need to use SystemVerilog for design and validation of my project. Any idea which version of Modelsim supports both design and validation subset of sytemverilog well? I used VCS before and trying to find it if I can use Modelsim instead of VCS for simulation.

Thanks in advance!

Answer 1

According to this table, ModelSim supports SystemVerilog design features, but not verification features. This means that it probably does not support classes, randomization, or the coverage features of SV.

The latest simulator platform from Mentor Graphics is branded Questa. This is really just an extension to Modelsim. Questa has full support for SystemVerilog. This is what you want if you have (or can get) a license for it. My experience is that EDA simulators are licensed in a tiered manner, so some features may only be available if you have a certain license.

The Questa simulator marketing page is at http://www.mentor.com/products/fv/questa/

Answer 2

You are with the student version, so try one of this list.

I guess there isn't an open source simulator, let us know if you find something.

other option you can use other things like myhdl check out this as well.

Answer 3

ModelSim 10.1d supports SystemVerilog except for SystemVerilog coverage, SystemVerilog assertions, randomize() method, and program blocks. The student version and Altera-Starter versions are free.

ModelSim 10.1d can be used for verification. Most verification engineers are using UVM library, and ModelSim can run UVM.

A trivial UVM testbench for ModelSim