system-verilog

Hardware design with VHDL or Verilog is more like programming nowadays. However, I see SO members are not so actively talking about VHDL/Verilog programming. Is there any forum dealing with hardware design with Verilog/VHDL/SystemVerilog or SystemC? Prof. Falken Logic Design was closed because of too little attention. It's now reopened, but interest remains low. comp.lang.vhdl http://groups.google.com/group/comp.lang.vhdl/ I haven't actively read it in a couple years, but I recall it being a great source, with some very knowledgeable and helpful people. Looking at it now it appears to be

I'd like to set a parameter based on a parameter which is set when the module is instantiated. I have the following. module foo #(WORDS = 8); parameter P00 = 33; logic [7:0] tmp; generate case (WORDS) 4: begin : A assign tmp = 8'haa; parameter P00 = 4; end 8: begin : B assign tmp = 8'hbb; parameter P00 = 8; end 16: begin : C assign tmp = 8'hcc; parameter P00 = 16; end default: begin : D assign tmp = 8'hdd; parameter P00 = 8; end endcase endgenerate initial begin $display ("WORDS = %d", WORDS); $display ("tmp = %h", tmp); $display ("P00 = %d", P00); end endmodule I expected to get an error for

I've got a register declared as so: logic signed [15:0][2:0][15:0] registers; When I place a 2's compliment number into the array and arithmetically shift the number, it logical shifts instead: registers[0][0] = 16'b1000000000000000; registers[0][0] = registers[0][0]>>>2; Apparently, the system will logical shift instead of arithmetically shift if the number is not signed. However as you can clearly see, 'registers' is definitely signed. Does anybody know what I might be missing here? Thanks! With Verilog, once you take a part-select, the result is unsigned . Use the $signed system task on the

Problem Description : I design in SystemVerilog and write the testbenches in the same language. I want to be able to compile my design and test different functions during simulation in the way you would using an interpreter with e. Ideally, I would have a terminal pop-up upon simulation when the simulator hit some line. Potential Ideas : I've looked at the DPI-C and it seems like I would have to "export" all tasks in my project in order to run them from the interpreter. However, I'm not sure how to do this automatically or if there's a better way. Furthermore, I have no idea how I would get C

I'm trying to create a multi-stage comparator in verilog and I can't figure out how to increment multiple genvars in a single generate loop. I'm trying the following: genvar i,j; //Level 1 generate j=0; for (i=0;i<128;i=i+1) begin: level1Comp assign ci1[i] = minw(tc[j],tc[j+1]); j = j+2; end endgenerate And getting the following error: Error-[SE] Syntax error Following verilog source has syntax error : "encoder.v", 322: token is '=' j=0; Anyone know how to increment multiple genvars in the same generate statement? Or at least get equivalent functionality? Assuming that ci1 has half the depth

What is the difference between $size and $bits operator in verilog.? if I've variables, [9:0]a , [6:0]b , [31:0]c . c <= [($size(a)+$size(b)-1]-:$bits(b)]; What will be the output at 'c' from the above expression? $size shall return the number of elements in the dimension, which is equivalent to $high - $low + 1 . It is relative to the dimension, not only bit counts. If the type is 1D packed array or integral type, it is equal to $bits . $bits system function returns the number of bits required to hold an expression as a bit stream. $bits ( [expression|type_identifier] ) It returns 0 when

Is it possible to write a function that can detect the input data width automatically? For example, consider the parity function below: function parity; input [31:0] data; parity = ^ data; endfunction When parity(data) is called, the input data should be limited to 32 bits. Alternatively, one could write a macro, such as `PARITY(data) in which the system function $bits can detect the width of data and make the macro width-independent. Is it possible to have the same flexibility for functions? Edit: I need my code to be synthesizable. You can create a parameterized function. See section 13.8 in