How does a system verilog structure be realized in hardware? are the members declared as wires?

问题

I have seen lots of system verilog program examples representing packets of data as a packed structure. Does this data travel serially like a packet? How does a system verilog structure be realized in hardware?

回答1:

A packed structure in SystemVerilog simply gives you an alternative way to access fields of a signal by name instead of by bit position. For example

typedef struct packed {
     logic [2:0] field1; // 3-bits
     logic [4:0] field2; // 5-bits
} signal_t; // 8-bits

You can now declare either a wire or variable with that type

wire signal_t sigA;
var signal_t sigB;

(the var keyword is implicit is most places except in a port declaration)

You can now access field1 as either sigA[7:5] or sigA.field1.

Unpacked structures, as nguthrie points out, provide a hierarchical grouping of variables, but they also provide a stronger types than Verilog. See my application note on this.

回答2:

Structures are just a convenient way of encapsulating variables. It is a way to show that these variables should be operated on as a group. However, calling something a packet is not going to get the synthesizer to create the hardware that you want. It is up to you to create the logic for the protocol that you are dealing with.

来源：https://stackoverflow.com/questions/21809877/how-does-a-system-verilog-structure-be-realized-in-hardware-are-the-members-dec