System Verilog fork join - Not actually parallel?

问题

I am learning system verilog and thought separate threads are created for each process in fork join. But I find if I have a while loop in my first process, my second process does not start which makes me think fork join is not actually parallel.

class A;

task run();
$display("A started");
while(1);
endtask

endclass

class B;

task run();
$display("B started");
endtask

endclass

Class C;

task run();
fork
   A.run();
   B.run(); 
join
endtask

endclass

My output is

 Class A started

and the program is running forever. I thought it should print

 Class A started
 Class B started

and run forever. Could someone point out what I am missing here? Thanks

回答1:

SystemVerilog Fork..Join statement creates processes that are parallel only in the simulation sense. But the processes are not parallel in the multicore sense -- the processes will not be executed on multiple threads of a processor. These processes would be scheduled on the execution queue at the same simulation time stamp. But these would be executed on a single logical CPU, and therefor from the CPU perspective they would be executed sequentially. In your code example, both class A and B run tasks are scheduled to be executed at the same simulation time. When the SystemVerilog simulator comes across the Fork..Join statement, it puts them on the execution queue. When you ran the simulation, your simulator started A.run first. And since A.run process goes into and infinite loop that does not yield, the simulator did not get a chance to execute B.run. Note that if you have multiple tasks scheduled at the same simulation time, the SystemVerilog LRM does not dictate which task would be executed first. Some other simulator might have executed B.run before starting A.run.

回答2:

You can put #0 delay in while(1), to let the second take its turn:

task run();
$display("A started");
while(1) #0;
endtask

来源：https://stackoverflow.com/questions/24922227/system-verilog-fork-join-not-actually-parallel

标签

multithreading

system-verilog