system-verilog

问题 I want to initialize a parameterized array parameter as follow: parameter n = 4; parameter [(log2(n)-1):0] state [(n-1):0] = '{2'h3, 2'h2, 2'h1, 2'h0}; // for n=4 This assignment works fine if n=4. When n=8, it should initialize as {3'h7, 3'h6, 3'h5, 3'h4, 3'h3, 3'h2, 3'h1, 3'h0} I want to initialize it like this: for(i=0,i<n,i=i+1) state[i] = i; Now what should I use to do this initialization? Can I do it with generate? Here log2 is a function. 回答1: First off, you are using SystemVerilog,

问题 I'm new to verilog and I am doing a project for my class. So here is my code: wire [n-1:0] subcounter_of_counter; reg [n-1:0] mask,free; //subcounter_of_counter: dinei ena vector apo poious subcounter apoteleitai o counter(id) always @(*) begin //command or id or mask or free or subcounter_of_counter if (command==increment) begin for (int i = 0; i < n; i=i+1)begin if (i<id) begin subcounter_of_counter[i]=1'b0; end else if (i==id) begin subcounter_of_counter[i]=1'b1; end else begin if( (|mask

问题 I'm trying to override a sequence by instance. An example code will describe it best: class my_vir_seq extends base_vir_seq; my_seq_c seq1, seq2; `uvm_object_utils_begin(my_vir_seq) `uvm_field_object(seq1, UVM_ALL_ON) `uvm_field_object(seq2, UVM_ALL_ON) `uvm_object_utils_end `uvm_declare_p_sequencer(v_seqr) function new(string name = "my_vir_seq"); super.new(name); endfunction // new virtual task body(); `uvm_do_on(seq1, p_sequencer.my_seqr) `uvm_do_on(seq2, p_sequencer.my_seqr) endtask //

问题 In the below module, ideally cnt, width & start should be inout port, instead of output port. But I tried with those ports as output ports and still I am able to run it without any error. So can inout and output ports be used interchangeably in Verilog? If no, then what is the exact criteria, where inout port must be used (output port can't be used in that case)? module (clk, rst, cnt, start, width, signal); input clk, rst, signal; output reg [11:0] cnt, width; output reg start; always @

问题 I have an always process running in my testbench that calls $urandom_range() Is it possible to reseed this while im running my testbench? I guess it has something to do with srandom but can't get it to work. 回答1: It is possible to seed the random number generator for the thread (ie that used by $urandom etc) by calling $urandom with an integer argument, eg: $urandom(12345); You mention srandom . This is another way to interact with the thread’s random number generator and that is by using the

问题 Can I have groups inside a struct? pseudo-code: typedef struct { input_group { logic a; } output_group { logic b; } } my_signals_list 回答1: Short answer: no. If you want to have signals grouped like this, why not create a struct for the input group and a struct for your output group? typedef struct { logic a; } input_group_s; typedef struct { logic b; } output_group_s; typedef struct { input_group_s input_group; output_group_s output_group; } my_signals_list; As Greg points out in the comments

问题 I am new to UVM and I am trying to verify a memory design where I am trying to run a write sequence multiple times followed by read sequence same number of times so that I could read the same addresses I am writing to, and compare. For this I tried to create a new class extended from uvm_object with a queue to store the addresses I am writing to, so that I could use them in read seq and I am instantiating this class in the scoreboard and then sending the handle of class to the read sequence

问题 I met a problem when trying to write this assertion. I tried to assert the scenario that signal B must be true at least 1 occurrence after signal A is true. The assertion I wrote is below: example : assert property( @(posedge clk) disable iff(reset) A |-> ##[0:$] B[->1]) else `uvm_error(....) The problem is, if during the simulation signal B is never be true after A is true, the uvm_error is not executed. I expected it to be executed, and the simulation reports the message: example: started

问题 I am pretty new to Verilog, but would like to understand it properly. Currently I am making TxRx on FPGA. I noticed that my code is consuming huge amount of logic, although it should not be like that. So I did not wrote my code properly. I know where is mistake, obviously my for loop is making parallelization of expressions (especially because this for loop is nested into another for loop). What would be right way to write code to avoid this. The code is working but it is not efficient. Feel

问题 I'm quite a novice to Verilog, but I have an array of 16-elements (each element is 16-bits long) and I wish to find the minimum entry the array, return the minimum, and re-arrange all the entries in the array that come after the minimum so that the array is one contiguous block of entries. I know I have to use a comparator, but I really have no idea where to start with regards to comparing a large group of numbers and determining the minimum. EDIT: What I'm actually making is a priority queue