system-verilog

问题 Hello Friends I still not know how to Generate Delay in Verilog For synthesis and call it any line in Verilog for synthesis...for finding this I write a code but it not works please help me if you know how to Generate Delay and call in any line like a C's Function* ......Actually Friends if you tell me why I use for Loop here then my answer is - I want to move pointer inside for loop until and unless they completes its calculation that I made for Delay Generation .. module state_delay; reg

问题 would an always block with no sensitivity list infer a combinational logic, just the same as always_comb or always @(*) ? Eg code: always begin if (sig_a)begin @(posedge sig_b); // wait for a sig_b posedge event @(negedge sig_b); // then wait for a sig_b negedge event event_true=1; end if (event_true)begin @((sig_c==1)&&(sig_a==0)); //wait for sig_a to deassert and sig_c assert event to be true yes =1; end else yes =0; end 回答1: Synthesis tools require a specific template coding style to

问题 I have to implement randomize() function in systemVerilog because the tool I use (model sim) doesn't support this function. I implemented a basic function in a class with the following member: bit [15:0] data_xi; bit [15:0] data_xq; the basic random function: //function my_randomize function int my_randomize(int seed); int temp1, temp2; temp1 = (($urandom(seed)) + 1); data_xi = temp1 - 1; temp2 = (($urandom(seed)) + 1); data_xq = temp2 - 1; if(temp1 != 0 || temp2 != 0 ) return 1; else return

问题 I am trying to debug my code shown below. I am fairly new to SystemVerilog and hopefully I can learn from this. Let me know of any suggestions. The errors I am receiving are: Error-[ICPD] Invalid procedural driver combination "divide.v", 2 Variable "Q" is driven by an invalid combination of procedural drivers. Variables written on left-hand of "always_comb" cannot be written to by any other processes, including other "always_comb" processes. "divide.v", 2: logic [7:0] Q; "divide.v", 8: always

问题 Is there a way in Verilog or SystemVerilog to insert generate statement inside case statement to generate all the possible input combinations. For example a typical use case would be for a N:1 mux. case(sel) generate for(i = 0; i < N; i += 1) i: out = q[i]; endgenerate endcase I tried this, but the tool gives error. An alternate syntax is available which is out <= q[sel]; But, my tool is not understanding this(the mux is fully decoded) and generating combinational loops. I can use if

问题 I have a few assertions that use the triggered property of sequences. This is useful for checking properties of the form "when X happens, Y must have happened sometime in the past". Let's take a simple example: Given three signals, a , b and c , c is only allowed to go high if a was high 3 cycles ago and b was high 2 cycles ago. This is a trace that satisfies this property: To be able to check this, we'd need a helper (clocked) sequence that should match at the point where a c is legal:

问题 I would like to write a module with a variable number of inputs, i.e. depending on some parameter, the result would be: module my_module #(LENGTH)( input clk, input rst_n, input [LENGTH-1:0] data_1 ); //... endmodule or module my_module #(LENGTH)( input clk, input rst_n, input [LENGTH-1:0] data_1, input [LENGTH-1:0] data_2, input [LENGTH-1:0] data_3 ); //... endmodule Would it be possible to do this in Verilog or Systemverilog or would I have to write a script, let's say in Python, in order

问题 I am using RedHat EL 4. I am using Bash 3.00.15. I am writing SystemVerilog and I want to emulate stdin and stdout. I can only use files as the normal stdin and stdout is not supported in the environment. I would like to use named pipes to emulate stdin and stdout. I understand how to create a to_sv and from_sv file using mkpipe, and how to open them and use them in SystemVerilog. By using "cat > to_sv" I can output strings to the SystemVerilog simulation. But that also outputs what I'm

问题 According to 1800-2012 specs, Queue::delete( [input int index] ) deletes an element of a queue in SystemVerilog, furthermore, a Queue can perform the same operations as an unpacked Array, giving it access to: Array::find_first_index( ) which returns the index of the first element matching a certain criteria. i.e. find_first_index( x ) with ( x == 3) Now I'd like to delete a unique item, guaranteed to exist, from the Queue. Combining 1 and 1 gives me: queue.delete(queue.find_first_index( x )

问题 I am getting an error to compile code line 9, so I am not sure how to dynamically access arrays. I have to build logic [255:0] from the received bytes . (Looks like I have to review data types of SystemVerilog :( ). Thanks in advance. module test; task test_array (logic [7:0] B); static logic [255:0] l_ar_B; l_ar_B[7:0] = B; for(int i=0; i<32; i++) l_ar_B[(i*8+7) : (i*8)] = B; // Error-[IRIPS] Illegal range in part select $stop(); endtask initial begin $display("Start"); test_array(8'h11);