system-verilog

问题 Is it possible to write a function that can detect the input data width automatically? For example, consider the parity function below: function parity; input [31:0] data; parity = ^ data; endfunction When parity(data) is called, the input data should be limited to 32 bits. Alternatively, one could write a macro, such as `PARITY(data) in which the system function $bits can detect the width of data and make the macro width-independent. Is it possible to have the same flexibility for functions?

问题 Looking at some code I'm maintaining in System Verilog I see some signals that are defined like this: node [range_hi:range_lo]x; and others that are defined like this: node y[range_hi:range_lo]; I understand that x is defined as packed, while y is defined as unpacked. However, I have no idea what that means. What is the difference between packed and unpacked vectors in System Verilog? Edit: Responding to @Empi's answer, why should a hardware designer who's writing in SV care about the

问题 Is it possible and/or useful to ever use a continuous assignment in a Verilog procedure? For example, would there ever be any reason to put an assign inside of an always block? For example this code: always @(*) begin assign data_in = Data; end Furthermore would it be possible to generate sequential logic with this approach? always @(posedge clk) begin assign data_in = Data; end 回答1: It is called procedural continuous assignment . It is the use of an assign or force (and their corresponding

问题 Is it possible and/or useful to ever use a continuous assignment in a Verilog procedure? For example, would there ever be any reason to put an assign inside of an always block? For example this code: always @(*) begin assign data_in = Data; end Furthermore would it be possible to generate sequential logic with this approach? always @(posedge clk) begin assign data_in = Data; end 回答1: It is called procedural continuous assignment . It is the use of an assign or force (and their corresponding

问题 I understood that System verilog does not have very good regular expression support inbuilt. How can I check in systemVerilog that a srting matches to the following regular expressions: "\d+(ns|ps|us)" 回答1: You have a number of different options. Some simulators already support a set of SystemVerilog string method extensions that handle regular expressions such as str.match() and str.search(). result = str.match(“pattern”); // returns true if the pattern is matched with the str. If you are

问题 I want to execute always block at time zero. For e.g. below code won't execute at time zero. always @* begin //functional code end I moved sensitivity list at the end so that code will execute at time zero, always begin //funcitonal code @*; end This code executes at time zero but does not execute at all after time zero, even if there is a change in inputs used inside the block. For example see the code below and its output: module AlwaysTimeZeroTest_v(); reg reg_A; initial begin $display ("I

问题 I made some tests in some EDA playground, to check what simulator tools are reporting when in a module some inputs are driven. Here is eda playground link : https://www.edaplayground.com/x/5qK4 So from my experiment the only way the tool is reporting some error when doing such thing is using the var keyword when defining the input. Can someone explain why there is difference between the three different way to declare the input ? I guess that means you can do port coercion when declaring it as

问题 The following verilog source code and/or testbench works nicely across commercial simulators, iverilog as well as formal verification tool (yosys-smtbmc) Please keep the complaint about `ifdef FORMAL until later. I need them to use with yosys-smtbmc which does not support bind command yet. I am now debugging the generate coding since the multiplication (using modified baugh-wooley algorithm) does not work yet. When o_valid is asserted, the multiply code should give o_p = i_a * i_b = 3*2 = 6

问题 I'm trying to instantiate some modules in Verilog using a generate block since I'm going to be instantiating a variable amount of them. genvar i; generate for (i=1; i<=10; i=i+1) begin status whatever_status ( .clk(clk), .reset_n(reset_n), .a(a[i]), .b(b[i]), .out(out[i]) ); end endgenerate a & b are declared as input arrays to the parent module and out is declared as a array of wires. What am I doing wrong here? Is this not allowed in Verilog? Quartus is telling me: Error (10644): Verilog

问题 My code is a sequential structure, 8 constant taps, 8 bit FIR. I used a memory to save all the input*taps, but I keep getting and error while trying to save these multiplications. I compiled it on Modelsim and got "syntax error". After, I tried iverilog and got "syntax error" and "error: Invalid module instantiation". I feel like I'm missing something really obvious but couldn't solve it. The code goes as follows: /* Código de um filtro FIR 8 taps, 8 bits Aluno: Rafael Menezes Start date: 19