Driving module input | 易学教程

问题

I made some tests in some EDA playground, to check what simulator tools are reporting when in a module some inputs are driven.

Here is eda playground link : https://www.edaplayground.com/x/5qK4

So from my experiment the only way the tool is reporting some error when doing such thing is using the var keyword when defining the input.

Can someone explain why there is difference between the three different way to declare the input ?

I guess that means you can do port coercion when declaring it as wire

I post the code here as well

module test(
  input var logic a,
  input logic b,
  input c
);

assign a = 1'b0;
assign b = 1'b0;
assign c = 1'b0;

endmodule

回答1:

This is an input variable of type logic:

 input var logic a,

There's no debate about that because each is explicitly declared*.

Section 23.2.2.3 of IEEE 1800-2012 says (the port kind is var or wire):

If the port kind is omitted: — For input and inout ports, the port shall default to a net of default net type. The default net type can be changed using the `default_nettype compiler directive

Therefore, because the default default_nettype is wire, this is an input wire of type logic:

input logic b,

Section 23.2.2.3 of IEEE 1800-2012 also says:

If the data type is omitted, it shall default to logic except for interconnect ports which have no data type

Therefore this is an input wire of type logic:

input c

Now it is certainly illegal to drive a variable from an assign statement if it is already driven from somewhere else, so this line is definitely no good:

assign a = 1'b0;

Because input a is definitely a variable - that is explicit. But if we change that to (say)

always_comb a = 1'b0;

then it's still no good, because the input is considered to be driving the variable a using an assign statement and, as we already know, it is illegal to drive a variable from an assign statement if it is already driven from somewhere else.

However, because b and c are nets (of kind wire), it is fine to drive them from more than one place, so these lines should be OK:

assign b = 1'b0;
assign c = 1'b0;

*No project was ever late because the typing too too long. Therefore, why not just do this?

来源：https://stackoverflow.com/questions/53179282/driving-module-input

标签

verilog

system-verilog