system-verilog

问题 I have a serial output of a verilog module I'd like to testbench using system-verilog. The output, called 'SO' will output something like 8'hC6 given the correct serial input 'SI' with a value of say 8'h9A. Is there an easy way to encode / decode serial IOs without having to explicitly describe each signal? For example: assert property @(posedge clk) $rose(EN) |-> ##[1:3] SI ##1 !SI[*2] ##1 SI[*2] ##1 !SI ##1 SI ##1 !SI ##[1:3] SO[*2] ##1 !SO[*3] ##1 SO[*2] ##1 !SO; It looks like a jumbled

问题 I am clock gating some latch and logic in my design. I don't have much experience in synthesis and place & route. What is the proper way to implement clock gating in RTL? Example1: always_comb begin gated_clk = clk & latch_update_en; end always_latch begin if(gated_clk) begin latch_data <= new_data; end end Example2: I stumbled into a RTL examples while doing some research about good practices in RTL clock gating. That example implemented the above code like this: clock_gator cg_cell (.clk

问题 I have tried to design a Booth multiplier and it runs well in all compilers including: Modelsim,Verilogger Extreame,Aldec Active Hdl & Xilinx's Isim. ..... I know Simulation and Synthesis are two Different Process and only few Verilog constructs with various restrictions are there for synthesis. But I don't know what happen While loop in my program not work in Synopsys Synplify 9.6 as well as in Xilinx ise 14.2 . When I try to synthesize Synopsys says "loop iteration limit 2000 exceeded"

问题 I think the question sums it up pretty well as to what I want: passing the value of a variable to a macro in SystemVerilog. For example, what I want: Say, there are 4 signals by the name of abc_X_def and I want to initialize all of them to 0. So, without macros: abc_0_def = 4'b0000; abc_1_def = 4'b0000; abc_2_def = 4'b0000; abc_3_def = 4'b0000; Now, the code that I have written is having a problem: `define set_value(bit) abc_``bit``_def = 4'b0000 for (int i = 0; i < 4; i++) begin `set_value(i

问题 I am trying to create a for loop that assigns different values to a logic array given the iteration of the loop. So, for instance, let's say I am trying to instantiate two different bricks, both with a width of 10 and height of 5. Let's also say that each of these values are 10 bits. For two bricks, I have the code: logic[19:0] Brick_Width; logic[19:0] Brick_Height; Where the first brick's width and height will be assigned into the most significant 10 bits and the second's in the least

问题 What functions do I need to call to use Regular Expressions in Systemverilog/UVM? Note: I'm not asking how to use regular expressions, just method names. 回答1: First, if you want to use regular expression, you'll need to make sure you're using a UVM library compiled together with its DPI code (i.e. the UVM_NO_DPI define isn't set). The methods you want to use are located in dpi/uvm_regex.svh . The main function is uvm_re_match(...) , which takes as an argument a regular expression and the

问题 I am trying to create a module which switches x input data packets to a single output packet according to a one hot input. If x was a fixed value of 4, I would just create a case statement, case (onehot) 4'b0001 : o_data = i_data[0]; 4'b0010 : o_data = i_data[1]; 4'b0100 : o_data = i_data[2]; 4'b1000 : o_data = i_data[3]; default : o_data = 'z; endcase But with variable x, how do I define all cases? Thanks. 回答1: parameter X = 4; input [X-1:0] onehot; input i_data [X]; output reg o_data;

问题 I've got a register declared as so: logic signed [15:0][2:0][15:0] registers; When I place a 2's compliment number into the array and arithmetically shift the number, it logical shifts instead: registers[0][0] = 16'b1000000000000000; registers[0][0] = registers[0][0]>>>2; Apparently, the system will logical shift instead of arithmetically shift if the number is not signed. However as you can clearly see, 'registers' is definitely signed. Does anybody know what I might be missing here? Thanks!

问题 I've got a register declared as so: logic signed [15:0][2:0][15:0] registers; When I place a 2's compliment number into the array and arithmetically shift the number, it logical shifts instead: registers[0][0] = 16'b1000000000000000; registers[0][0] = registers[0][0]>>>2; Apparently, the system will logical shift instead of arithmetically shift if the number is not signed. However as you can clearly see, 'registers' is definitely signed. Does anybody know what I might be missing here? Thanks!

问题 Problem Description : I design in SystemVerilog and write the testbenches in the same language. I want to be able to compile my design and test different functions during simulation in the way you would using an interpreter with e. Ideally, I would have a terminal pop-up upon simulation when the simulator hit some line. Potential Ideas : I've looked at the DPI-C and it seems like I would have to "export" all tasks in my project in order to run them from the interpreter. However, I'm not sure