system-verilog

问题 Signal driver_a is reassigned in the always block back to 0, but why is the always block not activating and assign value to driver_b ? always @(driver_a) begin driver_b = driver_a; driver_a = 0; end initial begin driver_a = 0; driver_b = 0; #2 driver_a = 8'h8; #2 driver_a = 8'hf; end In the waveform, I expect that after driver_a assigns its value to driver_b, then in the next line when driver_a gets assigned to 0, I'd expect the always block to reactivate and assign value 0 back to driver_b.

问题 Now I'm trying to digging the systemverilog as the below denaliCdn_ahbTransaction burst1; task sendTransfers; burst1= new; burst1.Direction = DENALI_CDN_AHB_DIRECTION_WRITE; burst1.FirstAddress = 32'h4020;//16416 M3 and M0 to S1 burst1.Kind = DENALI_CDN_AHB_BURSTKIND_INCR4; burst1.Size = DENALI_CDN_AHB_TRANSFERSIZE_HALFWORD; burst1.Data = new [8]; foreach (burst1.Data[ii]) burst1.Data[ii] = ii; void'(activeMaster1.transAdd(burst1,0)); .... endtask Especially, from here , how does ii be

问题 I am combining two designs into a single chip design. The RTL code is written in SystemVerilog for synthesis. Unfortunately, the two designs contain a number of modules with identical names but slightly different logic. Is there a namespace or library capability in SystemVerilog that would allow me to specify different modules with the same name? In other words is there a lib1::module1, lib2::module1 syntax I could use to specify which module I want? How is this sort of module namespace

问题 I create this code from this curcuit Image Here And this is Error image Image Here This curcuit is Quadruple Bus Transcievers with 3-state outputs Verilog Code module Q52QuadrupleBus3Stlate(GAB,GBA,A,B); inout [3:0] A,B; input GAB,GBA; reg winA,winB; assign B = (GAB==1&&GBA==0) ? winA : 4'hz; assign A = (GAB==0&&GBA==1) ? winB : 4'hz; always @ (GAB or GBA) begin winA <= A; winB <= B; end endmodule Test Bench `timescale 1ps / 1ps module Q52TestBench; reg GAB; reg GBA; // Bidirs wire [3:0] A;

问题 -This code is written in verilog using Modelsim 10.2d.The errors below indicate there is some problem with {cout,l3} assignment. module alu(a,b,bin,cin,op,cout,res); input [31:0] a,b; input [1:0] op; input bin,cin; reg [31:0] l1,l2,l3; output cout; output [31:0] res; assign l1 = a & b; assign l2 = a | b; initial if(bin == 1'b0) assign {cout,l3} = a + b + cin; else assign {cout,l3} = a - b + cin; mux4to1(l1,l2,l3,op,res); endmodule Error- v(14): LHS in procedural continuous assignment may not

问题 IEEE Std 1800™-2012 section 4.9.5 says "Switch processing shall consider all the devices in a bidirectional switch-connected net before it can determine the appropriate value for any node on the net because the inputs and outputs interact. A simulator can do this using a relaxation technique." What is this relaxation technique the LRM is referring to? Where can I read the detailed relaxation algorithm? 回答1: A bidirectional switch is inherently an analog device. Trying to simulate this kind of

问题 I was learning about the verilog stratified event queue. I had a minor doubt about the inactive events. I understood that they are carried out after all the active events are done with at the current simulation time. But I wrote a simple code to understand the concept better but the result I got is what confuses me. Here is the code I wrote: module main; int x; initial begin $monitor("x is %0d",x); #0 x = 5; // inactive event x = 3; // active event end endmodule RESULT : x is 3. According to

问题 I have installed fftw C library succefully on my linux system. Here is more info about fftw c => http://www.fftw.org/ I have a sample C code which can call fftw C functions successfully. Below is a C ccode and command to run the C code: Code: #include <stdio.h> #include <stdlib.h> #include <stdint.h> #include <math.h> #include <fftw3.h> int main(void) { double FFT_in[] = {0.1, 0.6, 0.1, 0.4, 0.5, 0, 0.8, 0.7, 0.8, 0.6, 0.1,0}; double *IFFT_out; int i,size = 12; fftw_complex *middle; fftw_plan

问题 How do I control the verbosity of certain components so that I can set a verbosity to only few of the components? Lets say, for example in the verification of a particular feature, the test, few set of components/sequences/objects/interfaces etc are involved. I would like to set the verbosity of only these to be UVM_HIGH . I do not want to set the global severity to be set UVM_HIGH since lot of unrelated debug messages could come in which might increase the log size. What would be a cleaner

问题 Following up on this question about the difference between packed and unpacked vectors in SV, why would I ever want to use unpacked vectors? Packed vectors have these advantages that unpacked vectors don't have: You can perform bit-wise operations on them You can perform arithmetic operations on them You can take slices of them You can copy them as a whole vector You can do anything you can with un packed vectors (to the best of my knowledge) What advantage do unpacked vectors have over