system-verilog

问题 I have registers instantiated in a Register block Regblock as such: DUT.Regblock.Register1 DUT.Regblock.RegisterA DUT.Regblock.RegisterABC ... All these registers have the same inner structure. I would like to simulate the effects of bit flips in these registers. //Here an attempt to do bit flips bitFlipLocation = $random; force DUT.RegBlock.Register1.reg[bitFlipLocation] = ~DUT.RegBlock.Register1.reg[bitFlipLocation]; release DUT.ABCStar1.RegBlock.Register1.reg[bitFlipLocation]; Is there a

问题 I want to call questa sim commands like add wave ,add list, write list from my SystemVerilog test bench task add_files_to_list(); add wave -position insertpoint sim:/top/clk add list sim:/top/clk write list -window .main_pane.list.interior.cs.body /home/simulation/top/example.lst endtask but the above doesn't work when i do from system verilog, i have to do i manually from tool. is there any way to do it. or can i call a tcl script from my system verilog code. Thanks 回答1: mti_fli::mti_Cmd(

问题 I have defined a structure with three integers, then created a dynamic array of the structure. Later in the code, I want to increment some of the integer values in the structure: typedef struct { integer tc; integer pass; integer fail; } score_t; score_t scorecard[]; integer tc_count; initial .... scorecard = new[`MAX_TC]; .... scorecard[tc_count].fail = 0; .... scorecard[tc_count].fail++; However, when I compile in Aldec Active-HDL I get the following error: Error: VCP2615 ../../../m3_test

问题 This is a follow-on question from How can I iteratively create buses of parameterized size to connect modules also iteratively created?. The answer is too complex to answer in a comment and the solution may be helpful for other SOs. This question is following the self-answer format. Addition answer are encouraged. The following code works and uses a bi-directional array. module Multiplier #(parameter M = 4, parameter N = 4)( input [M-1:0] A, //Input A, size M input [N-1:0] B, //Input B, size

问题 Now I'm trying to study about clss of systemverilog. From many class of example, I found the 'new' in 2 types. The case of the 'new' is existed in class. The case of the 'new' is existed in initial. Is there any difference between those implementation of constructor? One more, what is in the function new()? I'm not sure what purpose is in the function new() update For example 1 is. Class xxx ... Function new(); ... Endfunction Endclass Example2 is program class xxxx endclass Initial begin

问题 I'm using mailbox in a UVM SV test bench and facing some issue while trying to write in mailbox. My code looks like bellow: class my_seqyuence extends uvm_sequence; mailbox data; some_user_defined_type mydata; function new(string name = "my_sequence"); super.new(name); data=new(); endfunction task body(); forever begin // blocking-get. program is blocked here... not why get is not returning...! data.get(mydata); decode_mydata_and_do_something_here; end endtask function void writetrans(some

问题 Just started learning System Verilog. I am confused about the usage of statements always_ff and always_latch . The former would be used as: always_ff @ (posedge clk) begin a <= b; end while the latter: always_latch begin a <= b; end The first is activated just by the positive edge of the clock and coupled with non-blocking assignment produces a FF. The always_latch is obviously thought to represent a latch, but then why use a non-blocking assignment? Wouldn't be better using a always_comb

问题 I'm checking primality of a number in a form of 6n+1 or 6n-1. I have the below code, but it doesn't seem to be generated correct result. module prime(clk, rst, start, A, ready, P); input clk, rst, start; input [7:0] A; output ready, P; reg ready, P; reg [7:0] divisor; reg val; always @ (posedge clk or negedge rst) begin if (!rst) begin P <= 1'bx; end else if (start) begin case (A) -1 : P <= 1; 0 : P <= 1; 1 : P <= 1; 2 : P <= 1; 3 : P <= 1; 5 : P <= 1; endcase if (A%2 == 0 && A != 2) begin P

问题 So I would like to simulate a simple register file and test it. But it's been pretty confusing. I put together what I hope is a functional register file based on the notes that my professor provided, but now I'm struggling to create the test bench for it. I guess the main thing is how it has two DATA's and ADDR's (he showed an example of a memory file which only has one of each). Anyway, for my test bench I simply want to write some numbers to the register like in a for loop and instantiate

问题 For e.g. initial begin generate for(genvar i; i < 4; i++) //Code endgenerate end //initial I'm getting error using QuestaSim with the concept. "Near generate: syntax error, unexpected generate " 回答1: No. generate blocks are evaluated during elaboration time . While initial , always and other procedural blocks start at zero simulation time , that is, run-time. Referring to Systemverilog IEEE 1800-2012 : Generate schemes are evaluated during elaboration of the design . Although generate schemes