system-verilog

问题 This question already has answers here : What is `+:` and `-:`? (2 answers) Closed 5 months ago . I am seeing a code in SystemVerilog which has something like this: if(address[2*pointer+:2]) do_something; How should I understand the +: when indexing this vector? I found that it is called bit slicing, but I can't find an explanation about it. 回答1: Description and examples can be found in IEEE Std 1800-2012 § 11.5.1 "Vector bit-select and part-select addressing". First IEEE appearance is IEEE

问题 This question already has answers here : What is `+:` and `-:`? (2 answers) Closed 5 months ago . I am seeing a code in SystemVerilog which has something like this: if(address[2*pointer+:2]) do_something; How should I understand the +: when indexing this vector? I found that it is called bit slicing, but I can't find an explanation about it. 回答1: Description and examples can be found in IEEE Std 1800-2012 § 11.5.1 "Vector bit-select and part-select addressing". First IEEE appearance is IEEE

问题 I am always confusing while declaring an array and Array Querying Function in SystemVerilog. Can you explain me in details for given example: Example-1 integer matrix[7:0][0:31][15:0]; // 3-dimensional unpacked array of integers i am confuse in size // and dimension of given array for 1 and 2 dimension its easy to // understand but for 3 and 4-dimension its little bit confusing... Example-2 //bit [1:5][10:16] foo [21:27][31:38]; Example-3 //module array(); bit [1:5][10:16] foo1 [21:27][31:38]

问题 i have a module parameter that is an array of a predefined struct. I set the default size of this array as 1 element. The idea is to override it with the appropriate size at the time of instantiation. The way i show below doesn't override the size. It only overides the first value. I can see why it would do this as the size field is not parameterized. Is there a better way than to pass a parameter for the size? Thank you for the help. module reg_slave #(parameter reg_pkg::defval_pair [0:0]

问题 I'm trying to pass an interface to a module which is an array of interfaces. interface front_port #(parameter DATA_WIDTH = 4); logic [DATA_WIDTH - 1 : 0] data; logic acknowledge; modport f_interface(input data, output acknowledge); endinterface interface front_interface #(parameter NO_OF_IN_PORTS = 3); front_port front_ports[NO_OF_IN_PORTS](); endinterface module A #(parameter NO_OF_IN_PORTS = 3) ( interface front_port; ); module testbench; font_interface #(.NO_OF_IN_PORTS(3)) my_front

问题 I want to generate delay using counter, actually here I use counter to generate delay after each 1 Bit transfer, so that its better understand externally on fpga pin from which by SPI(serial) LCD is connected with it. Therefore I had created a shift register which shift 1 bit then gives delay then next bit(Bit-Delay-bit-delay..). Here is my code of counter: module spidelay( input wire clk, input wire enb, output reg sclkout ); reg [23:0] stmp; always @(posedge clk) begin if ( enb == 1 ) begin

问题 Now, I'm trying to make a coarse random signal not fine. So I'm using the $urandom command in the verilog. But still I can't get the coarse random signal. the below is the my random verilog code but I don't know how to get the a coarse random signal not fine. always@(clk) begin temp = $urandom; end EDIT coarse random signal means I can tell you by using adder signal. reg [29:0] temp; always@(posedge clk or negedge rst) begin if(!rst) temp <= 0; else temp <= temp + 1; end From here, we can see

问题 Is it true that with the contemporary advanced SV RTL simulators, the simulation footprint may increase when using unpacked arrays vs the packed arrays? If so, is this a problem and do verification teams insist on rules to use packed arrays? TIA. Sanjay 回答1: "[Does] the simulation footprint may increase when using unpacked arrays vs the packed arrays?" It depends on the simulator allocates and accesses its memory. Most cases packed arrays will have a smaller memory footprint then unpacked

问题 I am designing an FSM in SystemVerilog for synthesis through the QuartusII (14.1) tool to put on an Altera FPGA. I am using an enum declaration to make the code much more reasonable: typedef enum logic [7:0] { CMD_INIT, CMD_WAIT, CMD_DECODE, CMD_ILLEGAL, CMD_CMD0, ... } cmd_st; ... cmd_st cs, ncs; ... Whenever Quartus synthesized this state machine, it seems to create a one-hot encoding despite the logic [7:0] part of the type. As in, when I got to add the states to SignalTap, I get all of

问题 I am developing a SystemVerilog monitor that extends ovm_monitor and I'd like to know how to import the ovm macros that I am using. I am using: `ovm_component_utils_begin `ovm_field_string `ovm_component_utils_end I tried the following at the top of my file, both of which do not compile: import ovm_pkg::ovm_monitor; import ovm_pkg::ovm_macros; and import ovm_pkg::ovm_monitor; `include "ovm_macros.svh" VCS compile error: Error-[SE] Syntax error Following verilog source has syntax error : "my