how to get the a coarse random signal in the verilog not fine?

问题

Now, I'm trying to make a coarse random signal not fine. So I'm using the $urandom command in the verilog. But still I can't get the coarse random signal.

the below is the my random verilog code but I don't know how to get the a coarse random signal not fine.

always@(clk) begin

temp = $urandom;

end

EDIT

coarse random signal means I can tell you by using adder signal.

reg [29:0] temp;

always@(posedge clk or negedge rst) begin
if(!rst)
temp <= 0;
else
temp <= temp + 1;
end

From here, we can see temp[0] and temp[29] signals differences what i mean the coarse random signal have a change with enough change period but find random signal means like temp[0] is rapidly changed signal .

回答1:

OK, I can think of two ways of doing, both requires using the previous state of temp.

randomize(temp) with {foreach (temp[bitt]) temp[bitt] ^ const'(temp[bitt]) dist {1:=1, 0:=10};};

The above says for each bit of temp, the probability of a random bit being the same its current state is 10 times more likely than being different.

  randomize(temp) with {$countones(temp^const'(temp)) < 10;};

The above says the total number of bits that can be different from the current value is less that ten.

来源：https://stackoverflow.com/questions/43197205/how-to-get-the-a-coarse-random-signal-in-the-verilog-not-fine