问题
I understood that System verilog does not have very good regular expression support inbuilt.
How can I check in systemVerilog that a srting matches to the following regular expressions: "\d+(ns|ps|us)"
回答1:
You have a number of different options.
Some simulators already support a set of SystemVerilog string method extensions that handle regular expressions such as str.match() and str.search().
result = str.match(“pattern”); // returns true if the pattern is matched with the str.
If you are using the UVM, there is a DPI routine that does the same thing
result = uvm_pkg::uvm_re_match(“pattern”,str);
There are number of other packages out there such as SVunit that also provide the DPI routines for you.
来源：https://stackoverflow.com/questions/44948561/system-verilog-regular-expressions