How to generate pseudo random number in FPGA?

Question

How to generate pseudo random number in FPGA?

Answer 1

This has been covered (I'd go for an LFSR): Random number generation on Spartan-3E

Answer 2

There's an excellent Xilinx application note on generating pseudo-random number sequences efficiently in an FPGA. It's XAPP052.

Answer 3

If it's not for cryptography or other applications with an intelligent adversary (e.g. gambling) I'd use a linear feedback shift register approach.

It only uses exclusive or and shift, so it is very simple to implement in hardware.

Answer 4

As others have said, LFSRs can be used for pseudo random numbers in an FPGA. Here is a VHDL implementation of a maximal length 32-bit LFSR.

process(clk)

  -- maximal length 32-bit xnor LFSR based on xilinx app note XAPP210
  function lfsr32(x : std_logic_vector(31 downto 0)) return std_logic_vector is
  begin
    return x(30 downto 0) & (x(0) xnor x(1) xnor x(21) xnor x(31));
  end function;

begin
  if rising_edge(clk) then
    if rst='1' then
      pseudo_rand <= (others => '0');
    else
      pseudo_rand <= lfsr32(psuedo_rand);
    end if;
  end if;
end process;